AI00878C

11 0 An

A0

Qn

Q0

DATA OUT

D

S

Q

READ

S

WRITE

ADDR

OP

CODE

1 0

An

A0

DATA IN

D

Q

OP

CODE

Dn

D0

1

BUSY

READY

S

ERASE

WRITE

ENABLE

1

0

Xn X0

D

OP

CODE

1

01

S

ERASE

WRITE

DISABLE

1

0

Xn X0

D

OP

CODE

00

0

CHECK

STATUS

ADDR

Figure 6. READ, WRITE, EWEN, EWDS Sequences

Erase

The Erase instruction (ERASE) programs the ad-

dressed memory byte or word bits to ’1’. Once the

address is correctly decoded, the falling edge of the

Chip Select input (S) starts a self-timed program-

ming cycle.

If the ST93C46 is still performing the write cycle,

the Busy signal (Q = 0) will be returned if S is driven

high, and the ST93C46 will ignore any data on the

bus. When the write cycle is completed, the Ready

signal (Q = 1) will indicate (if S is driven high) that

the ST93C46 is ready to receive a new instruction.

Write

The Write instruction (WRITE) is followed by the

address and the 8 or 16 data bits to be written. Data

input is sampled on the Low to High transition of

the clock. After the last data bit has been sampled,

Chip Select (S) must be brought Low before the

next rising edge of the clock (C), in order to start

the self-timed programming cycle. If the ST93C46

is still performing the write cycle, the Busy signal

Notes: 1. An: n = 5 for x16 org. and 6 for x8 org.

2. Xn: n = 3 for x16 org. and 4 for x8 org.

7/13

ST93C46A/46C/46T, ST93C47C/47T