AI00879B

S

ERASE

11

D

Q

ADDR

OP

CODE

1

BUSY

READY

CHECK

STATUS

S

ERASE

ALL

10

D

Q

OP

CODE

1

BUSY

READY

CHECK

STATUS

00

An

A0

Xn X0

ADDR

Figure 7. ERASE, ERAL Sequences

(Q = 0) will be returned if S is driven high, and the

ST93C46 will ignore any data on the bus. When the

write cycle is completed, the Ready signal (Q = 1)

will indicate (if S is driven high) that the ST93C46

is ready to receive a new instruction.

The Write instruction includes an automatic Erase

cycle before writing the data, it is therefore unnec-

essary to execute an Erase instruction before a

Write instruction execution.

Erase All

The Erase All instruction (ERAL) erases the whole

memory (all memory bits are set to ”1”). A dummy

address is input during the instruction transfer and

the erase is made in the same way as the ERASE

instruction above. If the ST93C46 is still performing

the write cycle, the Busy signal (Q = 0) will be

returned if S is driven high, and the ST93C46 will

ignore any data on the bus. When the write cycle

is completed, the Ready signal (Q = 1) will indicate

(if S is driven high) that the ST93C46 is ready to

receive a new instruction.

Write All

For correct operation, an ERAL instruction should

be executed before the WRAL instruction.

The Write All instruction (WRAL) writes the Data

Input byte or word to all the addresses of the

memory. In the WRAL instruction, NO automatic

erase is made so all bytes/words must be erased

before the WRAL instruction. If the ST93C46 is still

performing the write cycle, the Busy signal (Q = 0)

will be returned if S is driven high, and the ST93C46

will ignore any data on the bus. When the write

cycle is completed, the Ready signal (Q = 1) will

indicate (if S is driven high) that the ST93C46 is

ready to receive a new instruction.

Notes: 1. An: n = 5 for x16 org. and 6 for x8 org.

2. Xn: n = 3 for x16 org. and 4 for x8 org.

INSTRUCTIONS (cont’d)

8/13

ST93C46A/46C/46T, ST93C47C/47T