Symbol

Alt

Parameter

Test Condition

Min

Max

Unit

Protect Enable Valid to Clock High

50

ns

Write Enable Valid to Clock High

50

ns

Chip Select High to Clock High

50

ns

Input Valid to Clock High

100

ns

Clock High to Input Transition

100

ns

Clock High to Output Low

500

ns

Clock High to Output Valid

500

ns

Clock Low to Protect Enable Transition

0

ns

Chip Select Low to Write Enable Transition

250

ns

Clock Low to Chip Select Transition

0

ns

Chip Select Low to Chip Select High

Note 1

250

ns

Chip Select High to Output Valid

500

ns

Chip Select Low to Output Hi-Z

300

ns

Clock High to Clock Low

Note 2

250

ns

Clock Low to Clock High

Note 2

250

ns

Erase/Write Cycle time

10

ms

Clock Frequency

0

1

MHz

2. The Clock frequency specification calls for a minimum clock period of 1

must be greater or equal to 1

PRE

W

C

S

D

OP CODE

OP CODE

START

START

OP CODE INPUT

tCHDX

tDVCH

tSHCH

tCLCH

tCHCL

tWVCH

tPRVCH

AI00887

Figure 4. Synchronous Timing, Start and Op-Code Input

4/16

ST93CS66, ST93CS67