TAS5701PAP datasheet(17/26 Pages) TI

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Clock, Auto Detection, and PLL

SERIAL DATA INTERFACE

PWM SECTION

SERIAL INTERFACE CONTROL AND TIMING

I2S Timing

TAS5701

www.ti.com ...................................................................................................................................................................................................... SLOS559 – JUNE 2008

The 12-V supply should be from a low-noise, low-output-impedance voltage regulator. Likewise, the 18-V

power-stage supply is assumed to have low output impedance and low noise. The power-supply sequence is not

critical as facilitated by the internal power-on-reset circuit. Moreover, the TAS5701 is fully protected against

erroneous power-stage turnon due to parasitic gate charging.

The TAS5701 digital audio processor (DAP) is a clock slave device. It accepts MCLK, SCLK, and LRCLK.

The TAS5701 checks to verify that SCLK is a specific value of 32-fs, 48- fs, or 64-fs. The DAP only supports a 1 ×

fs LRCLK. The timing relationship of these clocks to SDIN1and SIN2 is shown in subsequent sections. The clock

section uses MCLK or the internal oscillator clock (when MCLK is unstable or absent) to produce the internal

clock.

The DAP can auto-detect and set the internal clock control logic to the appropriate settings for the frequencies of

32 kHz, normal speed (44.1 or 48 kHz), double speed (88.2 kHz or 96 kHz), and quad speed (176.4 kHz or 192

kHz).

Serial data is input on SDIN1 and SIN2. The PWM outputs are derived from SDIN1 ands SIN2. The TAS5701

DAP accepts 32-, 44.1-, 48-, 88.2-, 96-, 176.4-, and 192-kHz serial data in 16-, 18-, 20-, or 24-bit data in

left-justified, right-justified, and I2S serial data formats. See Table 1 for format control settings.

SDIN1 left channel data is sent to OUTA/OUTB configured in BTL. SDIN1 right channel data is sent to

OUTC/OUTD. SDIN2 left channel data is sent to SUB_PWM+/–. The right channel data of SDIN2 is ignored.

The DAP (digital audio processor) has three channels of high-performance digital PWM modulators that are

designed to drive bride-tied output H-bridge configurations with BD modulation.

The DAP uses noise-shaping and sophisticated error correction algorithms to achieve high power efficiency and

high-performance digital audio reproduction. The DAP uses a fourth-order noise shaper to provide >100-dB SNR

performance from 20 Hz to 20 kHz.

The PWM section accepts 24-bit PCM data from the DAP and outputs three PWM audio output channels. The

PWM section output supports bridge-tied loads ONLY.

The PWM section has individual channel dc blocking filters that are ALWAYS enabled. The filter cutoff frequency

is less than 1 Hz.

Finally, the PWM section has a fixed maximum modulation limit of 97.7%.

I2S timing uses LRCLK to define when the data being transmitted is for the left channel and when it is for the

right channel. LRCLK is low for the left channel and high for the right channel. A system clock (SCLK) running at

32, 48, or 64 × fs is used to clock in the data. There is a delay of one bit clock from the time the LRCLK signal

changes state to the first bit of data on the data lines. The data is written MSB first and is valid on the rising edge

of the bit clock. The DAP masks unused trailing data bit positions.

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