AD2S1210

Rev. 0 | Page 7 of 36

Parameter

Description

Unit

Delay WR/FSYNC rising edge to SDO high-Z

15

ns min

Delay from SAMPLE before WR/FSYNC falling edge

ns min

Delay CS falling edge to WR/FSYNC falling edge in normal mode

2

ns min

A0 and A1 setup time before WR/FSYNC falling edge

2

ns min

A0 and A1 hold time after WR/FSYNC falling edge2

In normal mode, A0 = 0, A1 = 0/1

ns min

In configuration mode, A0 = 1, A1 = 1

ns min

Delay WR/FSYNC rising edge to WR/FSYNC falling edge

10

ns min

Frequency of SCLK input

20

MHz

25

MHz

15

MHz

16 bits of position/velocity data. If the fault information is not required, A0/A1 may be released following 16 clock cycles.