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AD2S1210ASTZ 数据表(PDF) 21 Page - Analog Devices |
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AD2S1210ASTZ 数据表(HTML) 21 Page - Analog Devices |
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21 / 36 page  AD2S1210 Rev. 0 | Page 21 of 36 REGISTER MAP Table 10. Register Map Register Name Register Address Register Data Read/Write Register Position 0x80 D15 to D8 Read only 0x81 D7 to D0 Read only Velocity 0x82 D15 to D8 Read only 0x83 D7 to D0 Read only LOS Threshold 0x88 D7 to D0 Read/write DOS Overrange Threshold 0x89 D7 to D0 Read/write DOS Mismatch Threshold 0x8A D7 to D0 Read/write DOS Reset Max Threshold 0x8B D7 to D0 Read/write DOS Reset Min Threshold 0x8C D7 to D0 Read/write LOT High Threshold 0x8D D7 to D0 Read/write LOT Low Threshold 0x8E D7 to D0 Read/write Excitation Frequency 0x91 D7 to D0 Read/write Control 0x92 D7 to D0 Read/write Soft Reset 0xF0 D7 to D0 Write only Fault 0xFF D7 to D0 Read only POSITION REGISTER Table 11. 16-Bit Register Address Bit Read/Write 0x80 D15 to D8 Read only 0x81 D7 to D0 Read only The position register contains a digital representation of the angular position of the resolver input signals. The values are stored in 16-bit binary format. The value in the position register is updated following a falling edge on the SAMPLE input. Note that with hysteresis enabled (see the Control Register section), at lower resolutions, the LSBs of the 16-bit digital output are set to zero. For example, at 10-bit resolution, Data Bit D15 to Data Bit D6 provide valid data; D5 to D0 are set to zero. With hysteresis disabled, the value stored in the position register is 16 bits regardless of resolution. At lower resolutions, the LSBs of the 16-bit digital output can be ignored. For example, at 10-bit resolution, Data Bit D15 to Data Bit D6 provide valid data; D5 to D0 can be ignored. VELOCITY REGISTER Table 12. 16-Bit Register Address Bit Read/Write 0x82 D15 to D8 Read only 0x83 D7 to D0 Read only The velocity register contains a digital representation of the angular velocity of the resolver input signals. The value in the velocity register is updated following a falling edge on the sample input. The values are stored in 16-bit, twos complement format. The maximum velocity that the AD2S1210 can track for each resolution is specified in Table 1. For example, the maximum tracking rate of the AD2S1210 at 16 bits resolution, with an 8.192 MHz input clock, is ±125 rps. A velocity of +125 rps results in 0x7FFF being stored in the velocity register; a velocity of −125 rps results in 0x8000 being stored in the velocity register. The value stored in the velocity register is 16 bits regardless of resolution. At lower resolutions, the LSBs of the 16-bit digital output should be ignored. For example, at 10-bit resolution, Data Bit D15 to Data Bit D6 provide valid data; D5 to D0 should be ignored. The maximum tracking rate of the AD2S1210 at 10-bit resolution with an 8.192 MHz input clock is ±2500 rps. A velocity of +2500 rps results in 0x1FF being stored in Bit D15 to Bit D6 of the velocity register; a velocity of −2500 rps results in 0x3FF being stored in Bit D15 to Bit D6 of the velocity register. In this 10-bit example, the LSB size of the velocity output is 4.88 rps. LOS THRESHOLD REGISTER Table 13. 8-Bit Register Address Bit Read/Write 0x88 D7 to D0 Read/write The LOS threshold register determines the loss of signal threshold of the AD2S1210. The AD2S1210 allows the user to set the LOS threshold to a value between 0 V and 4.82 V. The resolution of the LOS threshold is seven bits, that is, 38 mV. Note that the MSB, D7, should be set to 0. The default value of the LOS threshold on power-up is 2.2 V. DOS OVERRANGE THRESHOLD REGISTER Table 14. 8-Bit Register Address Bit Read/Write 0x89 D7 to D0 Read/write The DOS overrange threshold register determines the degradation of signal threshold of the AD2S1210. The AD2S1210 allows the user to set the DOS overrange threshold to a value between 0 V and 4.82 V. The resolution of the DOS overrange threshold is seven bits, that is, 38 mV. Note that the MSB, D7, should be set to 0. The default value of the DOS overrange threshold on power-up is 4.1 V. DOS MISMATCH THRESHOLD REGISTER Table 15. 8-Bit Register Address Bit Read/Write 0x8A D7 to D0 Read/write The DOS mismatch threshold register determines the signal mismatch threshold of the AD2S1210. The AD2S1210 allows the user to set the DOS mismatch threshold to a value between 0 V and 4.82 V. The resolution of the DOS mismatch threshold is seven bits, that is, 38 mV. Note that the MSB, D7, should be set to 0.The default value of the DOS mismatch threshold on power-up is 380 mV. |
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