AD2S1210

Rev. 0 | Page 9 of 36

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

48 47 46 45 44 43 42 41 40 39 38 37

35

DOS

34

LOT

33

RESET

30

B

31

NM

32

DIR

36

A1

29

A

28

DB0

27

DB1

25

DB3

26

DB2

2

CS

3

RD

4

WR/FSYNC

7

CLKIN

6

5

DGND

1

RES1

8

XTALOUT

9

SOE

10

SAMPLE

12

DB14/SDI

11

DB15/SDO

13 14 15 16 17 18 19 20 21 22 23 24

PIN 1

AD2S1210

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 4. Pin Function Descriptions

Pin

No.

Mnemonic

Description

1

RES1

Resolution Select 1. Logic input. RES1 in conjunction with RES0 allows the resolution of the AD2S1210 to be

programmed. Refer to the Configuration of AD2S1210 section.

2

CS

Chip Select. Active low logic input. The device is enabled when CS is held low.

3

RD

Edge-Triggered Logic Input. When the SOE pin is high, this pin acts as a frame synchronization signal and output

enable for the parallel data outputs, DB15 to DB0. The output buffer is enabled when CS and RD are held low. When

the SOE pin is low, the RD pin should be held high.

4

WR/FSYNC

Edge-Triggered Logic Input. When the SOE pin is high, this pin acts as a frame synchronization signal and input

enable for the parallel data inputs, DB7 to DB0. The input buffer is enabled when CS and WR/FSYNC are held low.

When the SOE pin is low, the WR/FSYNC pin acts as a frame synchronization signal and enable for the serial data bus.

5, 19

DGND

Digital Ground. These pins are ground reference points for digital circuitry on the AD2S1210. Refer all digital input

signals to this DGND voltage. Both of these pins can be connected to the AGND plane of a system. The DGND and

AGND voltages should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

6

voltages ideally should be at the same potential and must not be more than 0.3 V apart, even on a transient basis.

7

CLKIN

Clock Input. A crystal or oscillator can be used at the CLKIN and XTALOUT pins to supply the required clock frequency of

the AD2S1210. Alternatively, a single-ended clock can be applied to the CLKIN pin. The input frequency of the AD2S1210 is

specified from 6.144 MHz to 10.24 MHz.

8

XTALOUT

Crystal Output. When using a crystal or oscillator to supply the clock frequency to the AD2S1210, apply the crystal

across the CLKIN and XTALOUT pins. When using a single-ended clock source, the XTALOUT pin should be

considered a no connect pin.

9

SOE

Serial Output Enable. Logic input. This pin enables either the parallel or serial interface. The serial interface is selected

by holding the SOE pin low, and the parallel interface is selected by holding the SOE pin high.

10

SAMPLE

Sample Result. Logic input. Data is transferred from the position and velocity integrators to the position and velocity

registers, after a high-to-low transition on the SAMPLE signal. The fault register is also updated after a high-to-low

transition on the SAMPLE signal.

11

DB15/SDO

Data Bit 15/Serial Data Output Bus. When the SOE pin is high, this pin acts as DB15, a three-state data output pin

controlled by CS and RD. When the SOE pin is low, this pin acts as SDO, the serial data output bus controlled by CS and

WR/FSYNC. The bits are clocked out on the rising edge of SCLK.

12

DB14/SDI

Data Bit 14/Serial Data Input Bus. When the SOE pin is high, this pin acts as DB14, a three-state data output pin controlled

by CS and RD. When the SOE pin is low, this pin acts as SDI, the serial data input bus controlled by CS and WR/FSYNC. The

bits are clocked in on the falling edge of SCLK.