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STE100 数据表(PDF) 22 Page - STMicroelectronics

部件名 STE100
功能描述  PCI 10/100 ETHERNET CONTROLLER WITH INTEGRATED PHY 5V
PDF  66 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STE100 数据表(HTML) 22 Page - STMicroelectronics

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STE10/100
22/66
31~17
---
Reserved
16
LPCO
Lost Packet Counter Overflow
1: when lost packet counter overflow occurs. Cleared after
read.
0
RO/LH
15~0
LPC
Lost Packet Counter
The counter is incremented whenever a packet is discarded as
a result of no host receive descriptors being available. Cleared
after read.
0
RO/LH
CSR9(offset = 48h), SPR - Serial port register
31~15
---
Reserved
14
SRC
Serial EEPROM Read Control
When set, enables read access from EEPROM, when SRS
(CSR9 bit 11) is also set.
0
R/W
13
SWC
Serial EEPROM Write Control
When set, enables write access to EEPROM, when SRS
(CSR9 bit 11) is also set.
0
R/W
12
---
Reserved
11
SRS
Serial EEPROM Select
When set, enables access to the serial EEPROM (see
description of CSR9 bit 14 and CSR9 bit 13)
0
R/W
10~4
---
Reserved
3
SDO
Serial EEPROM data out
This bit serially shifts data from the EEPROM to the STE10/
100.
1RO
2
SDI
Serial EEPROM data in
This bit serially shifts data from the STE10/100 to the
EEPROM.
1
R/W
1
SCLK
Serial EEPROM clock
High/Low this bit to provide the clock signal for EEPROM.
1
R/W
0
SCS
Serial EEPROM chip select
1: selects the serial EEPROM chip.
1
R/W
CSR11(offset = 58h), TMR -General-purpose Timer
31~17
---
Reserved
16
COM
Continuous Operation Mode
1: sets the general-purpose timer in continuous operating
mode.
0
R/W
15~0
GTV
General-purpose Timer Value
Sets the counter value. This is a count-down counter with a
cycle time of 204us.
0
R/W
CSR13(offset = 68h), WCSR –Wake-up Control/Status Register
31
---
Reserved
Table 6. Control/Status register description
Bit #
Name
Descriptions
Default Val
RW Type



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