1/29

STE100P

January 2000

This is preliminary information on a new product now in development. Details are subject to change without notice.

1.0 DESCRIPTION

The STE100P, also referred to as STEPHY1, is a

high performance Fast Ethernet physical layer inter-

face for 10BASE-T and 100BASE-TX applications.

It was designed with advanced CMOS technology to

provide a Media Independent Interface (MII) for easy

attachment to 10/100 Media Access Controllers

(MAC) and a physical media interface for 100BASE-

TX of IEEE802.3u and 10BASE-T of IEEE802.3.

The STEPHY1 supports both half-duplex and full-du-

plex operation, at 10 and 100 Mbps operation. Its op-

erating mode can be set using auto-negotiation,

parallel detection or manual control. It also allows for

the support of auto-negotiation functions for speed

and duplex detection.

2.0 FEATURE

2.1 Industry standard

n

IEEE802.3u 100BASE-TX and IEEE802.3

10BASE-T compliant

n

Support for IEEE802.3x flow control

n

IEEE802.3u Auto-Negotiation support for

10BASE-T and 100BASE-TX

n

MII interface

n

Standard CSMA/CD or full duplex operation

supported

PQFP64

ORDERING NUMBER: STE100P

PRODUCT PREVIEW

10/100 FAST ETHERNET 3.3V TRANSCEIVER

Figure 1. BLOCK DIAGRAM

NRZ ToManchester

E ncoder

10 TX

Filter

TRANSMITTER

10/100

Scrambler

Auto

Negotiation

4B/5B

NRZ To NRZI

Encoder

Link Pulse

Generator

Binary To MLT3

Encoder

RECEIVER

10/100

Parallel to

Serial

Descrambler

Code Align

4B/5B

NRZI To NRZ

Decoder

Serial to

Parallel

NRZ To Manchester

Encoder

Link Pulse

Detector

SMART

Squelch

10 TX Filter

Clock Recovery

Clock

Generation

System

Clock

Adaptive

Equalization

BaseLine

Wander

B inary ToMLT3

Decoder

Clock Recovery

REGISTERS

HW Config

Power Down

LEDS

RX Channel

TX Channel

TXP

TXN

RXP

RXN

MDC

MDIO

RXD[3:0]

RX_ER

RX_DV

RX_CLK

TX_CLK

TXD[3:0]

TX_ER

TX_EN

LEDS

HW

configuration

pins

10Mb/s

100Mb/s

100Mb/s

10Mb/s

Loopback