STE100P

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30

PWRDWN

I

Power Down. When High, forces STE100P into Power Down mode. This pin is

OR’ed with the Power Down bit (PR0:11). During the Power Down mode, TXP/

TXN outputs and all LED outputs are 3-stated, and the MII interface is isolated.

5

4

3

2

1

MF0

MF1

MF2

MF3

MF4

I

Multi -Function pins. Each MF pin internally drives different configuration

functions. The functions of the five MF inputs are as follows:

The logic level of MF0-4 will determine the value that the affected bits will have

upon reset of the STE100P. The operating functions of CFG0, CFG1, and FDE

change depending on the state of MF0 (Auto-Negotiation enabled or disabled).

Table 2 shows the relationship between CFG0, CFG1 and FDE .

6

FDE

I

Full-D uplex Enable.

When A/N is enabled, FDE determines full-duplex advertisement capability in

combination with CFG0 and CFG1. (See Table 2)

When A/N is disabled, FDE directly affects full-duplex operation and determines

the value of PR0 bit 8 (Full/Half Duplex Mode Select).

When FDE is High, full-duplex is enabled and PR0:8 = 1.

When FDE is Low, full-duplex is disabled and PR0:8 = 0.

Digital Power Pins

38, 45, 64

VCCE, VCCE/I

7, 25, 39, 50

GNDE, GNDE/I

Analog Power Pins

9, 13, 16, 17, 22

VCCA

8, 10, 14, 20, 24

GNDA

Table 1. Pin Description

Pin No.

Name

Type

Description

Pin

Function

Register & Bit Affected

MF0

Auto-Negotiation

PR0:12 ANE

MF1

Enable NRZ-NRZI conversion

PR19:7 ENRZI

MF2

4B/5B Coding Enable

PR19:6 EN4B5B

MF3

Scrambler Operation Disable

PR19:0 DISCRM

mf4

MF4 10/100 Mbps Speed Select

PR0:13 SPSEL