USBLC6-4

Technical information

9/13

2.6

PSPICE model

Figure 16. shows the PSPICE model of one USBLC6-4SC6 cell. In this model, the diodes

are defined by the PSPICE parameters given in Figure 17.

Figure 16.

PSPICE model

Note:

This simulation model is available only for an ambient temperature of 27 °C.

MODEL = Dlow

MODEL = Dhigh

MODEL = Dlow

MODEL = Dhigh

MODEL = Dlow

MODEL = Dhigh

MODEL = Dlow

MODEL = Dhigh

VBUS

LIO

io1

RIO

LIO

io2

GND

RIO

LIO

RIO

io3

MODEL = Dzener

LIO

RIO

LIO

io4

RIO

RGND

LGND

MODEL = Dlow

MODEL = Dhigh

MODEL = Dlow

MODEL = Dhigh

MODEL = Dlow

MODEL = Dhigh

MODEL = Dlow

MODEL = Dhigh

VBUS

LIO

io1

RIO

LIO

io2

GND

RIO

LIO

RIO

io3

MODEL = Dzener

LIO

RIO

LIO

io4

RIO

RGND

LGND

Figure 17.

PSPICE parameters

Figure 18.

USBLC6-4SC6 PCB layout

considerations

0.1u

0.1u

0.1u

TT

0.6

0.6

0.6

VJ

0.42

0.63

0.38

RS

0.3333

0.3333

0.3333

M

1.24

1.13

1.62

N

100p

100p

100p

ISR

3.21p

2.27f

55.2p

IS

2.42

0.018

0.038

IKF

1m

1m

1m

IBV

20p

2.4p

2.4p

CJ0

7.3

50

50

BV

Dzener

Dhigh

Dlow

0.1u

0.1u

0.1u

TT

0.6

0.6

0.6

VJ

0.42

0.63

0.38

RS

0.3333

0.3333

0.3333

M

1.24

1.13

1.62

N

100p

100p

100p

ISR

3.21p

2.27f

55.2p

IS

2.42

0.018

0.038

IKF

1m

1m

1m

IBV

20p

2.4p

2.4p

CJ0

7.3

50

50

BV

Dzener

Dhigh

Dlow

50m

RGND

430p

LGND

100m

RIO

710p

LIO

50m

RGND

430p

LGND

100m

RIO

710p

LIO

D+1

C

= 100nF

BUS

D-1

GND

USBLC6-4SC6

D+2

D-2

1