Device description

L6911E

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5.2

Digital to analog converter

The built-in digital to analog converter allows the adjustment of the output voltage from

1.050V to 1.825V with 25mV binary steps as shown in the previous Table 6: VID Setting on

page 9. The internal reference is trimmed to ensure the precision of 1%.

The internal reference voltage for the regulation is programmed by the voltage identification

(VID) pins. These are TTL compatible inputs of an internal DAC that is realised by means of

a series of resistors rpoviding a partition of the internal voltage reference. The VID code

drives a multiplexer that selects a voltage on a precise point of the divider. The DAC output

is delivered to an amplifier obtaining the VPROG voltage reference (i.e. the set-point of the

error amplifier). Internal pull-ups are provided (realized with a 5

µA current generator); in this

way, to program a logic "1" it is enough to leave the pin floating, while to program a logic "0"

it is enough to short the pin to GND.

The voltage identification (VID) pin configuration also sets the power-good thresholds

(PGOOD) and the over- voltage protection (OVP) thresholds.

5.3

Soft start and inhibit

constant current, as shown in Figure 4 on page 13

wave inferior limit) also the upper MOS begins to switch and the output voltage starts to

increase.

The VSS growing voltage initially clamps the output of the error amplifier, and consequently

VOUT linearly increases, as shown in Figure 4 on page 13. In this phase the system works

in open loop. When VSS is equal to VCOMP the clamp on the output of the error amplifier is

released. In any case another clamp on the non-inverting input of the error amplifier remains

active, allowing to VOUT to grow with a lower slope (i.e. the slope of the VSS voltage, see

Figure 4 on page 13). In this second phase the system works in closed loop with a growing

reference. As the output voltage reaches the desired value VPROG, also the clamp on the

error amplifier input is removed, and the soft start finishes. Vss increases until a maximum

value of about 4V.

The Soft-Start will not take place, and the relative pin is internally shorted to GND, if both

VCC and OCSET pins are not above their own Turn-On thresholds; in this way the device

starts switching only if both the power supplies are present. During normal operation, if any

under-voltage is detected on one of the two supplies, the SS pin is internally shorted to GND

and so the SS capacitor is rapidly discharged.

The device goes in INHIBIT state forcing SS pin below 0.4V. In this condition both external

MOSFETS are kept OFF.