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L6911E 数据表(PDF) 24 Page - STMicroelectronics |
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L6911E 数据表(HTML) 24 Page - STMicroelectronics |
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24 / 34 page ![]() VRM demo board description L6911E 24/34 6 VRM demo board description Figure 12 shows the schematic circuit of the VRM evaluation board. The design has been developed for a VRM 8.5 Flexible Motherboard applicaton delivering up to 28.5A. An additional circuit sense a Vtt bus (1.2V typ.) and generate a 2.5mS (typ.) delayed Vtt_PWRGD signal when this rail is over 1.1V. The assertion of the Vtt_PWRGD signal enables the device together with the ENOUT input. Figure 12. Schematic circuit L6911E CONNECTOR EVALUATION KIT REV. 1.1 L2 L1 R7 R8 R9 C1-3 C10 C4-9 C17 Q3,Q4,Q5 Q1,Q2 D2 C12 F1 16 17 13 14 2 4 5 6 7 8 U1 L6911E +5 VIN +12Vcc VOUTCORE Vss 10 15 9 3 20 18 11 19 12 1 VCC GND VID0 VID1 VID2 VID3 VID4 SS OSC OCSET UGATE PHASE LGATE PGND PGOOD VSEN R3 R4 R5 R2 C18 C19 C20 VID0 VID1 VID2 VID3 VID25mV C11 D1 R6 R1 Vtt_PGOOD UZ TLC7701 8 2 4 7 3 5 6 1 OUTEN Vtt_sense Vdd NOT RESIN GND SENSE CT NOT RESET CONTROL RESET R14 C15 R12 Q6 R10 R11 C16 C14 Q7 C13 R13 D3 PWRGD R15 |
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