| 数据搜索系统,热门电子元器件搜索 |
|
TDA7502 数据表(PDF) 11 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
TDA7502 数据表(HTML) 11 Page - STMicroelectronics |
|
11 / 25 page ![]() TDA7502 SAI interface 11/25 3 SAI interface Figure 4. SAI timings Note: TDSP = dsp master clock cycle time = 1/FDSP Figure 5. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0 Table 11. Cycles Timing Description Value Unit tsckr Minimum Clock Cycle 4TDSP ns tdt SCKR active edge to data out valid 10 ns tlrs LRCK setup time 5 ns tlrh LRCK hold time 5 ns tsdid SDI setup time 15 ns tsdih SDI hold time 15 ns tsckph Minimum SCK high time 0.35 tsckr ns tsckpl Minimum SCK low time 0.35 tsckr ns VALID SDI0-3 VALID tsckph tsckpl tlrh tlrs tdt LRCKR SCKR (RCKP=0) tsdih tsckr tsdis D02AU1357 LEFT LSB(n-1) MSB(word n) MSB-1 (n) MSB-2 (n) LRCKR (#23) SCKR (#24) SDI0,1,2 (#20, #21, #22) RIGHT D02AU1358 |
|
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |