TDA7502 datasheet(16/25 Pages) STMICROELECTRONICS

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I2C timing

TDA7502

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I2C timing

Figure 15.

Definition of timing for the I2C bus.

tBUF

SDA

SCL

D02AU1371

tHD:STA

tSU:STA

tSU:STO

tHD:DAT

tSU:DAT

tLOW

tHIGH

tHD:STA

Table 14.

Definitions

Symbol

Parameter

Test condition

Standard

mode

I2C bus

Fast mode

I2C bus

Unit

Min.

Max.

Min.

Max.

FSCL

SCLl clock frequency

100

400

kHz

tBUF

Bus free between a STOP and Start

Condition

4.7

–

1.3

–

μs

tHD:STA

Hold time (repeated) START condition.

After this period, the first clock pulse is

generated

4.0

–

0.6

–

μs

tLOW

LOW period of the SCL clock

4.7

–

1.3

–

μs

tHIGH

HIGH period of the SCL clock

4.0

–

0.6

–

μs

tSU:STA Set-up time for a repeated start condition

4.7

–

0.6

–

μs

tHD:DAT DATA hold time

–

0.9

μs

Rise time of both SDA and SCL signals

Cb in pF

–

1000

20+0.1Cb

300

Fall time of both SDA and SCL signals

Cb in pF

–

300

20+0.1Cb

300

tSU;STO Set-up time for STOP condition

–

0.6

–

μs

tSU:DAT Data set-up time

250

100

Capacitive load for each bus line

–

400

–

400

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