TDA7513T datasheet(30/84 Pages) STMICROELECTRONICS

30 / 84 page

Functional description

TDA7513T

30/84

3.3

PLL and IF counter section

The IC contains a frequency synthesizer and a loop filter for the radio tuning system. Only

one VCO is required to build a complete PLL system for FM and AM upconversion. For auto

search stop operation an IF counter system is available.

3.3.1

PLL frequency synthesizer block

The counter works in a two stages configuration. The first stage is a swallow counter with a

two-modulus (32/33) precounter. The second stage is an 11-bit programmable counter. The

circuit receives the scaling factors for the programmable counters and the values of the

reference frequency via I2C bus. The reference frequency is generated by an adjustable

internal (XTAL) oscillator followed by the reference divider. The reference and step-

frequencies are independently selectable (RC, PC). The phase-frequency detector outputs

switches the programmable current source. The loop filter integrates the latter to a DC

voltage. The current source values is programmable with 6 bits received via I2C bus (A, B,

CURRH, LPF). To minimize the noise induced by the digital part of the system, a special

guard area is implemented. The loop gain can be adjusted for different conditions by setting

the current values of the chargepump generator.

3.3.2

Frequency generation for phase comparison

The VCO signal is fed to a two-modulus counter (32/33) prescaler, which is controlled by a

5-bit divider (A). A 5-bit register (PC0 to PC4) controls this divider. The output of the

prescaler is connected to an 11-bit divider (B), controlled by an 11-bit PC register (PC5 to

PC15).

The following expressions relate the divider output frequency (fSYN, forced by the loop to

equal the reference frequency at the phase comparator input fREF) to the VCO frequency

(fVCO) and to the crystal oscillator frequency (fXTAL):

fXTAL = (R+1) x fREF

fVCO = [33 x A + (B + 1 - A) x 32] x fREF

fVCO = (32 x B + A + 32) x fREF

Important: For correct operation: A

≤32; B ≥A

3.3.3

Three state phase comparator

The phase comparator generates a phase error signal according to phase difference

between fSYN and fREF. This phase error signal drives the charge pump current generator.

3.3.4

Charge pump current generator

This system generates correction current pulses with a polarity and a duration dictated by

the phase error signal. The current absolute values are programmable through register A for

high current and register B for low current.

The charge pump operates in high current mode when the phase difference between

between fSYN and fREF is high. The switch back to low current mode can be done either

automatically as a function of the inlock detector output (setting bit LDENA to "1") or via

software.

After reaching a phase difference equivalent to 10-40 ns (programmable) and a delay

multiple of 1/fREF, the chargepump is forced in low current mode. A new PLL divider

programming by I2C bus will switch the chargepump into high current mode.

TDA7513T 数据表(PDF) 30 Page - STMicroelectronics

TDA7513T 数据表(HTML) 30 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84

数据表下载