TDA7563A

I2C bus

23/35

7.6

Acknowledge

line during the acknowledge clock pulse, so that the SDA line is stable LOW during this clock

pulse.

(*) Transmitter

–

master (µP) when it writes an address to the TDA7563A

–

slave (TDA7563A) when the µP reads a data byte from TDA7563A

(**) Receiver

–

slave (TDA7563A) when the µP writes an address to the TDA7563A

–

master (µP) when it reads a data byte from TDA7563A

Figure 29.

Figure 30.

Figure 31.

Timing acknowledge clock pulse

SDA

SCL

DATA LINE

STABLE, DATA

VALID

CHANGE

DATA

ALLOWED

D99AU1031

SCL

SDA

START

STOP

D99AU1032

SCL

1

MSB

23789

SDA

START

ACKNOWLEDGMENT

FROM RECEIVER

D99AU1033