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STA309A 数据表(PDF) 22 Page - STMicroelectronics

部件名 STA309A
功能描述  Multi-channel digital audio processor with DDX
PDF  67 Pages
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制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

STA309A 数据表(HTML) 22 Page - STMicroelectronics

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Registers
STA309A
22/67
7.2
Register description
7.2.1
Configuration register A (0x00)
The DDX8000 supports sample rates of 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz,
176.4 kHz, 192 kHz, and 2.8224 MHz DSD. Therefore, the internal clocks are:
"
65.536 MHz for 32 kHz
"
90.3168 MHz for 44.1 kHz, 88.2 kHz, 176.4 kHz, and DSD
"
98.304 MHz for 48 kHz, 96 kHz, and 192 kHz
The external clock frequency provided to the XTI pin must be a multiple of the input sample
frequency (fs). The relationship between the input clock and the input sample rate is
determined by both the MCSn and the IRn (input rate) register bits. The MCSn bits
determine the PLL factor generating the internal clock and the IRn bits determine the
oversampling ratio used internally.
0x51
PSC1
RCV11
RCV10
RCV9
RCV8
RCV7
RCV6
RCV5
RCV4
0x52
PSC2
RCV3
RCV2
RCV1
RCV0
CNV11
CNV10
CNV9
CNV8
0x53
PSC3
CNV7
CNV6
CNV5
CNV4
CNV3
CNV2
CNV1
CNV0
Table 8.
Register summary (continued)
Addr
Name
D7
D6
D5
D4
D3
D2
D1
D0
76
54
321
0
COS1
COS0
DSPB
IR1
IR0
MCS2
MCS1
MCS0
10
00
001
1
Table 9.
MSC bits
Bit
RW
RST
Name
Description
0RW
1
MCS0
Master clock select: selects the ratio between the input
I2S sample frequency and the input clock.
1RW
1
MCS1
2RW
0
MCS2
Table 10.
MSC sample rates
Input sample rate
fs (kHz)
IR
MCS[2:0]
1XX
011
010
001
000
32, 44.1, 48
00
128 * fs
256 * fs
384 * fs
512 * fs
768 * fs
88.2, 96
01
64 * fs
128 * fs
192 * fs
256 * fs
384 * fs
176.4, 192
10
64 * fs
128 * fs
192 * fs
256 * fs
384 * fs
DSD
11
2 * fs
4 * fs
6 * fs
8 * fs
12 * fs



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