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ADE3800 数据表(PDF) 114 Page - STMicroelectronics |
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ADE3800 数据表(HTML) 114 Page - STMicroelectronics |
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114 / 138 page ![]() Register Description by Block ADE3800 114/138 ● Programmable output swing and common mode voltage ● Per channel programmable delay ● Programmable LVDS clock output polarity 4.19.1 Output Channels 128 Pin Package ● 16 channels dedicated RSDS; ● 10 channels shared by LVDS or RSDS — LVDS (1ppc): 4 data + 1 clock = 5 (others are unused) — LVDS (2ppc): 8 data + 2 clock = 10 — RSDS: 10 data (both 1ppc and 2ppc) 100 Pin Package ● 3 channels dedicated to RSDS, ● 10 channels shared by LVDS or RSDS — LVDS (1ppc): 4 data + 1 clock = 5 (others are unused) — LVDS (2ppc): 8 data + 2 clock = 10 — RSDS: 10 data (1ppc on channel A only) Table 41: LVDS/RSDS Registers (Sheet 1 of 5) Register Name Address Bits Mode Rst Description ANA_LVDSANA0 0060 [7] R/W 84 PLL Manual/Auto Select 0: manual (using ANA_LVDSANA0[1:0]) 1*: auto [6] R/W PLL Comparator Current Select 0*: 300uA (normal) 1: 200uA [5:4] R/W PLL Charge Pump Current Select 0*: 10uA (normal) 1: 25uA 2: 50uA 3: 100uA (fast response) [1:0] R/W PLL Manual Range Select (enabled by ANA_LVDSANA0[7]) 0*: 25uA (slowest) 1: 75uA 2: 125uA 3: 175uA (fastest) |
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