ADE3800 datasheet(35/138 Pages) STMICROELECTRONICS

部件名	ADE3800

功能描述	Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters

PDF	138 Pages

Scroll/Zoom	100%

制造商	STMICROELECTRONICS [STMicroelectronics]

网页	http://www.st.com

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ADE3800

Note:

All thresholds are in XCLK units.

SRT_VS_SEL

01EF

[5:4]

sclk div prescaler for SMEAS:

0*: 128

1: 256

2: 512

3: 1024

[3]

Bad csync threshold. Change SRT_CSYNC_THR until

this is stable low.

R/W

[2:0]

vert sync source select for re-sampling into inclk domain

for SMUX:

0*: VSYNC pin

1: vsync from composite HSYNC pin

2: vsync from composite SOG[0] comparator

3: vsync from composite SOG[1] comparator

4: vsync from composite SOG[2] comparator

5: filtered and delayed vsync (normal)

6: vsync from alt SOG source pin

7: reserved

SRT_COAST_RISE_HW_L

SRT_COAST_RISE_HW_M

SRT_COAST_RISE_HW_U

01F0

01F1

01F2

[7:0]

Shadow read back

SRT_COAST_FALL_HW_L

SRT_COAST_FALL_HW_M

SRT_COAST_FALL_HW_U

01F3

01F4

01F5

[7:0]

Table 16: Sync Retiming Registers (Sheet 2 of 2)

Addr

Mode

Bits

Rst

Description

ADE3800 数据表(PDF) 35 Page - STMicroelectronics

ADE3800 数据表(HTML) 35 Page - STMicroelectronics

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