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ADE3800 数据表(PDF) 15 Page - STMicroelectronics |
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ADE3800 数据表(HTML) 15 Page - STMicroelectronics |
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15 / 138 page  15/138 ADE3800 Pin Descriptions 23 32 XCLK I/O Crystal clock buffered output. Controlled by XCLK_EN pin 28 37 XCLK_EN I Crystal clock output enable. When connected to 3.3 V, the XCLK output is active When connected to Ground, the XCLK output is disabled 25 34 RESETN2 I Reset 2 inputa. Active Low 53 65 RESETN I Reset input1. Active Low 54 66 SDA I/O I2C Datab. Open drain 56 68 SCL/CSYNC I I2C Clockc or Composite Sync Input Signal 26 35 SDA2 I/O I2C 2 Data2. Open drain 27 36 SCL2/EXT_SOG/ CSYNC I I2C 2 Clock3 or Composite Sync Input Signal 24 33 TST_SCAN I Reserved for test. Should be connected to Digital Ground a. RESETN and RESETN2 pins are ORed together internally. The pin which is not used must be connected to ground. b. The SDA and SDA2 pins share the same internal bi-directional control. The pin that is not used reverts as output and must be left floating or connected to a pull-up resistor. c. This device has two RESET/I2C ports (RESETN/SCL/SDA or RESETN2/EXT_SOG/SDA2) to facilitate PCB layout. The state of the two RESET pins determines which RESET/I2C port is active. The RESET pin that is held in the low state disables that RESET/I2C port for normal RESET/I2C operations. However, the disabled ports SCL input (either SCL or EXT_SOG) can be used as a CSYNC input from an external CSYNC extractor. If this CSYNC input is not required, then the unused SCL pin should be connected to ground Table 6: Digital Section Power Supply Pins (Sheet 1 of 2) LQFP100 LQFP128 Name Description 5 4 DVDD18 Digital 1.8V Supply 6 5 DVDD18 Digital 1.8V Supply 7 6 DGND Digital Ground 8 7 DGND Digital Ground 18 27 DVDD18 Digital 1.8V Supply 19 28 DVDD18 Digital 1.8V Supply 20 29 DGND Digital Ground 21 30 DGND Digital Ground 22 31 DVDD33 Digital 3.3V Supply 55 67 DGND Digital Ground 57 69 DVDD33 Digital 3.3V Supply 66 78 DGND Digital Ground 67 DGND Digital Ground 68 79 DVDD18 Digital 1.8V Supply 69 80 DVDD18 Digital 1.8V Supply Table 5: System Controls (Sheet 2 of 2) LQFP100 LQFP128 Name Input/ Output Description |
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