 |
数据搜索系统，热门电子元器件搜索 |
|
|
数据搜索系统，热门电子元器件搜索 |
|
ADE3800XT 数据表(PDF) 101 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ADE3800XT 数据表(HTML) 101 Page - STMicroelectronics |
|
|
101 / 138 page  101/138 ADE3800 Register Description by Block Debug Mode If LVDS debug mode is enabled (omux_test[0] = 1), LVDS output data will be set to a static 7-bit pattern which is programmed in omux_ctrl4[6:0] If RSDS debug mode is enabled (omux_test[1] = 1), RSDS output data will be set to a static pattern which is programmed in omux_ctrl4[1:0]. 4.17.2 Output Clocks Output clock (to LVDS PLL) for both functional and test modes is the divide-by-2 clock generated inside omux. This clock is flopped on the falling edge of fsyn_outclk providing a ¼ phase offset between clock and data. RSDS output clocks 0 & 1 are set to fsyn_outclk_div2_dly for both functional and test modes. This clock has a programmable delay offset from the fsyn_outclk_div2. This is to ensure that data will meet the setup/hold requirements at the destination (panel.) The out_enab signal (from the TCON block) must be programmed so that its left (rising) edge is odd in 2 ppc RSDS mode. 4.17.3 Clock Sources and Timing Considerations The omux block operates on dotclk with the exception of omux_mux which runs on fsyn_outclk. Table 2.4 describes the relationship between fsyn_outclk, fsyn_outclk_div2 and dotclk. 70 58 TCON0 pwm_en ? pwm_b: tcon0 TCON SIGNALS pwm_en ? pwm_b: tcon0 TCON SIGNALS pwm_en ? pwm_b: tcon0 TCON SIGNALS 71 59 TCON1 pwm_en ? pwm_a: tcon1 pwm_en ? pwm_a: tcon1 pwm_en ? pwm_a: tcon1 72 60 TCON2 tcon2 tcon2 tcon2 73 61 TCON3 tcon3 tcon3 tcon3 74 62 TCON4 tcon4 tcon4 tcon4 75 63 TCON5 tcon5 tcon5 tcon5 76 64 TCON6 tcon6 tcon6 tcon6 77 65 TCON7 tcon7 tcon7 tcon7 Table 36: Clock relationship 1 ppc 2 ppc fsyn_outclk_freq 2x dotclk_freq dotclk_freq dotclk source sel fsyn_outclk_div2 half speed fsyn_outclk full speed GLBL_CLK_SRC_SEL_0[6:4] 2 3 GLBL_CLK_SRC_SEL_1[6:4] 3 3 FSYN_PR_OTCLK 2^22 * xclk_freq / dotclk_freq 2^21 * xclk_freq / dotclk_freq OUTPUT INTERFACE PIN # (LQFP 128) PIN # (LQFP 100) (RSDS INPUT NAME) PIN NAME OUTPUT MODE LVDS RSDS (LQFP-128) RSDS (LQFP-100) |
|
链接网址 |
| ALLDATASHEET是否为您带来帮助? [ DONATE ] |
关于 Alldatasheet | 广告服务 | 联系我们 | 隐私政策 | 数据表链接 | 链接交换 | 制造商名单 All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Chinese ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
