ADE3800XT datasheet(31/138 Pages) STMICROELECTRONICS

31 / 138 page

31/138

ADE3800

The digital loop filter is controlled by two parameters: A and B. The A and B parameters control the

response of the 2nd order digital filter. A and B are exponential coefficients. The relationship of

these numbers to the classic 2nd order damping and natural frequency are as follows:

● Damping = 2^(AE-8) * SQRT(5 * MFACTOR / (2^(BE+4)))

● Natural Frequency = SQRT(MFACTOR * 5 * 2^(BE-30))

Note:

Typical value for the A and B parameters is 66h.

The synthesized HSync supplied to SMUX is 50% duty cycle.

Table 15: Line Lock PLL Registers (Sheet 1 of 2)

Addr

Mode

Bits

Rst

Description

LLK_CTRL

0800

R/W

[6]

0*: use slow filter when coarse error is zero

1: use slow filter when lock condition is achieved

R/W

[5]

mfactor shadow control

0*: simple shadow. Apply new mfactor when mfactor_u

is written.

1: shadow transfer on in_venab falling edge.

R/W

[4]

0*: lock to rising edge of input HSync

1: lock to falling edge of input HSync

R/W

[3:1]

input HSync select

0*: HSYNC pin

1: SOG0

2: SOG1

3: SOG2

4: EXT_SOG

R/W

[0]

LLK pll free run enable

LLK_SYNC_OFFSET_MODE

0801

R/W

[3]

manual resync mode

The LLK pll requires a resync after any change of

mfactor or offset. Writing to this bit causes a one-time

resync of the PLL accumulator (cleared by H/W).

R/W

[2]

resync every frame modea

R/W

[1]

resync on in_venab falling edge1

R/W

[0]

resync on in_venab rising edge1

LLK_MFACTOR_L

0802

R/W

[7:0]

mfactor[7:0] = in_htotal

LLK_MFACTOR_U

0803

R/W

[3:0]

mfactor[11:8]

LLK_PHASE_RATE_INIT

0804

R/W

[7:0]

pll phase rate init

freq = xclk_freq * 128 / phase_rate_init.

LLK_TC_AEF

0805

R/W

[3:0]

time constant A when out of lock

LLK_TC_BEF

0806

R/W

[3:0]

time constant B when out of lock

LLK_TC_AES

0807

R/W

[3:0]

time constant A when in lock

LLK_TC_BES

0808

R/W

[3:0]

time constant B when in lock

LLK_LOCK_TOL

0809

R/W

[7:0]

error limit for determining lock. LSB = 150ps (typ)

LLK_LOCK_LINE_NB

080A

R/W

[7:0]

line count for determining lock.

- set when error is < lock_tol for lock_line_nb of lines.

- cleared if error exceeds lock_tol.

ADE3800XT 数据表(PDF) 31 Page - STMicroelectronics

ADE3800XT 数据表(HTML) 31 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载

链接网址

ADE3800XT 数据表(PDF) 31 Page - STMicroelectronics

ADE3800XT 数据表(HTML) 31 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表 下载

链接网址

数据表下载