ADE3800SXL datasheet(106/138 Pages) STMICROELECTRONICS

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ADE3800

106/138

Table 39: Register Map (Sheet 1 of 7)

Addr.

Bits

Mode

Rst

Description

TCON_CTRL

0B00

[6:4]

R/W

out_venab source selection

0*: out_venab generated from

out_enab (normal)

1: tcon_pgen

2: window venab[0]

3: window venab[1]

4: window venab[2]

5: window venab[3]

6-7: reserved

[3:2]

R/W

i2c block transfer (not tcon) event selection

0*: (hcount == 0) && (vcount == 0)

1: (hcount == 0)

2: srtd0

3: srtd1

[0]

R/W

TCON[7:0] output enable. Internal signals

are always active.

TCON_POLARITY_CTRL

0B01

[7:6]

R/W

vlen = toggle/polarity line sequence length

(desired – 1)

[5:4]

R/W

vtoggle / polarity horizontal reference (1 of

4 comparators)

[2:0]

R/W

polarity vmask selection

0*: pulse 0

1: pulse 1

2: pulse 2

3: pulse 3

4: pulse 4

5: pulse 5

6: pulse 0, reset vtog_count to 0 at rising

edge of vmask, polarity reset to 0

7: pulse 0, resync vtog_count to 1 at ris-

ing edge of vmask, polarity reset to 0

Note: pulse type must be vertical

TCON_INV_0

0B02

[7]

R/W

invert output tcon7

[6]

R/W

invert output tcon6

[5]

R/W

invert output tcon5

[4]

R/W

invert output tcon4

[3]

R/W

invert output tcon3

[2]

R/W

invert output tcon2

[1]

R/W

invert output tcon1

[0]

R/W

invert output tcon0

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