数据搜索系统,热门电子元器件搜索
  Chinese  ▼
ALLDATASHEETCN.COM

X  

ADE3800SXL 数据表(PDF) 34 Page - STMicroelectronics

部件名 ADE3800SXL
功能描述  Analog LCD Display Engine for XGA and SXGA Resolutions with Embedded LVDS and RSDS Transmitters
PDF  138 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
制造商  STMICROELECTRONICS [STMicroelectronics]
网页  http://www.st.com
标志 STMICROELECTRONICS - STMicroelectronics

ADE3800SXL 数据表(HTML) 34 Page - STMicroelectronics

Back Button ADE3800SXL Datasheet HTML 30Page - STMicroelectronics ADE3800SXL Datasheet HTML 31Page - STMicroelectronics ADE3800SXL Datasheet HTML 32Page - STMicroelectronics ADE3800SXL Datasheet HTML 33Page - STMicroelectronics ADE3800SXL Datasheet HTML 34Page - STMicroelectronics ADE3800SXL Datasheet HTML 35Page - STMicroelectronics ADE3800SXL Datasheet HTML 36Page - STMicroelectronics ADE3800SXL Datasheet HTML 37Page - STMicroelectronics ADE3800SXL Datasheet HTML 38Page - STMicroelectronics Next Button
Zoom Inzoom in Zoom Outzoom out
 34 / 138 page
background image
Register Description by Block
ADE3800
34/138
Table 16: Sync Retiming Registers (Sheet 1 of 2)
Register Name
Addr
Mode
Bits
Rst
Description
SRT_CSYNC_INV
01E0
R/W
[2]
00
invert vert sync signal extracted from internal SOG
comparator (sog_vs_inv)
R/W
R/W
[1]
invert vert sync extracted from composite sync signal on
HSync pin (csync_vs_inv)
R/W
[0]
invert filtered vert sync (filt_vs_inv)
SRT_CSYNC_THR_L
SRT_CSYNC_THR_U
01E1
01E2
R/W
R/W
[7:0]
[3:0]
80
00
composite sync vertical sync extractor threshold
(this is the narrowest HSync signal sent +50% as a
safety margin) refer to Figure 7
SRT_VSYNC_SEL
01E3
R/W
[2:0]
00
filtered vert sync source select
0*: VSYNC pin
1: vsync from composite HSYNC pin
2: vsync from composite SOG[0] comparator
3: vsync from composite SOG[1] comparator
4: vsync from composite SOG[2] comparator
5: vsync from alternate SOG source
6 - 7: Reserved
SRT_VSYNC_THR_L
SRT_VSYNC_THR_U
01E4
01E5
R/W
R/W
[7:0]
[3:0]
80
00
filtered vert sync delay
SRT_COAST_VS_SEL
01E6
R/W
[3]
00
coast signal trigger edge
0*: rising edge of selected VSync
1: falling edge of selected VSync
R/W
[2:0]
source selection for coast VSync trigger
0*: VSYNC pin
1: vsync from composite HSYNC pin
2: vsync from composite SOG[0] comparator
3: vsync from composite SOG[1] comparator
4: vsync from composite SOG[2] comparator
5: filtered and delayed vsync (normal)
6: vsync from alternate SOG source
7: Reserved
SRT_COAST_RISE_L
SRT_COAST_RISE_M
SRT_COAST_RISE_U
01E7
01E8
01E9
R/W
R/W
R/W
[7:0]
[7:0]
[7:0]
00
00
00
rising edge of coast, in XCLKs from vsync trigger
SRT_COAST_FALL_L
SRT_COAST_FALL_M
SRT_COAST_FALL_U
01EA
01EB
01EC
R/W
R/W
R/W
[7:0]
[7:0]
[7:0]
00
00
00
falling edge of coast, in XCLKs from vsync trigger
SRT_HS_CTRL
01EE
R/W
[4]
00
Edge of inclk on which to sample horizontal sync:
0*: rising edge
1: falling edge (normal)
R/W
[2:0]
HSync Sample Selection for SMUX
0*: reserved
1: llk_HSync (normal)
2: SOG0
3: SOG1
4: SOG2
5: EXT_SOG



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100  ...More


数据表 下载

Go To PDF Page


链接网址



ALLDATASHEET是否为您带来帮助?  [ DONATE ] 

关于 Alldatasheet   |   广告服务   |   联系我们   |   隐私政策   |   数据表链接    |   链接交换   |   制造商名单
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com