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ADE3800SXL 数据表(PDF) 21 Page - STMicroelectronics |
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ADE3800SXL 数据表(HTML) 21 Page - STMicroelectronics |
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21 / 138 page  21/138 ADE3800 Register Description by Block 4.3 Analog-to-Digital Converter (ADC) The Analog-to-Digital block has the following features: ● Supports input clocks up to 140MHz (SXGA 75Hz) ● Adjustable analog amplifier bandwidth ● Differential RGB input path for noise immunity ● Built-in Sync-on-Green support ● Individual RGB clock delay control ● Power down control ● Linear and independent Gain/Offset adjustment. GAIN CONTROL Red, Green, and Blue channels have independent control registers: ANA_ADC_RED_0, ANA_ADC_GRN_0, and ANA_ADC_BLU_0, respectively. FSYN_FM_AMPLITUDE 0855 R/W [7:0] 00 frequency modulation amplitude LSB = 4.5ps FSYN_FM_PERIODX64 0856 R/W [7:0] 80 frequency modulation period LSB = 1.184us FSYN_PULSE_HIGH_EXT 0857 R/W [7] 00 enable pulse extend 0*: disabled 1: enabled R/W [2:0] pulse extend value LSB = 0.3ns (typ) Table 11: FSYN_PR_SK Registers Register Name Addr Mode Bits Rst Description FSYN_PR_SK_0 FSYN_PR_SK_1 0860 0861 R/W R/W [7:0] [7:0] 00 00 sclk phase rate = 2^15 * xclk_freq / sclk_freq Set sclk = 140MHz i.e. FSYN_PR_SK_1/0 = 18AFh @ xclk = 27MHz Table 12: Clock Relationship 1 ppc 2 ppc FSYN_OUTCLK_FREQ 2x DOTCLK_FREQ DOTCLK_FREQ DOTCLK SOURCE SEL FSYN_OUTCLK_DIV2 (half speed) FSYN_OUTCLK (full speed) GLBL_CLK_SRC_SEL_0[6:4] 2 3 GLBL_CLK_SRC_SEL_1[6:4] 3 3 FSYN_PR_OTCLK 2^21 * XCLK_FREQ / 2x DOTCLK_FREQ 2^21 * XCLK_FREQ / DOTCLK_FREQ Table 10: FSYN Frequency Synthesizer Registers (Sheet 2 of 2) Register Name Addr Mode Bits Rst Description |
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