STPCI2GDY datasheet(79/111 Pages) STMICROELECTRONICS

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DESIGN GUIDELINES

Issue 1.0 - July 24, 2002

79/111

6.3.3. SDRAM

The STPC provides all the signals for SDRAM

control. Up to 128 MBytes of main memory are

supported. All Banks must be 64 bits wide. Up to 4

memory banks are available when using 16Mbit

devices. Only up to 2 banks can be connected

when using 64Mbit and 128Mbit components due

to the reallocation of CS2# and CS3# signals. This

is described in Table 6-4 and Table 6-5.

Graphics memory resides at the beginning of

Bank 0. Host memory begins at the top of graphics

memory and extends to the top of populated

SDRAM. Bank 0 must always be populated.

Figure 6-5, Figure 6-6 and Figure 6-7 show some

typical implementations.

The purpose of the serial resistors is to reduce

signal

oscillation

and

EMI

filtering

line

reflections. The capacitance in Figure 6-5 has a

filtering effect too, while it is used for propagation

delay compensation in the 2 other figures.

Figure 6-5. One Memory Bank with 4 Chips (16-bit)

CS0#

BA[1:0]

MA[12:0]

WE#

RAS0#

DQM[7:0]

MCLKI

MCLKO

DQM[7:6]

Reference Knot

CAS0#

MD[63:48]

DQM[5:4]

MD[47:32]

DQM[3:2]

MD[31:16]

DQM[1:0]

MD[15:0]

MD[63:0]

MCLKA

MCLKB

MCLKC

MCLKD

10pF

Length(MCLKI) = Length(MCLKy) with y = {A,B,C,D}

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