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STPCI2GDY 数据表(PDF) 61 Page - STMicroelectronics |
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STPCI2GDY 数据表(HTML) 61 Page - STMicroelectronics |
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61 / 111 page  ELECTRICAL SPECIFICATIONS Issue 1.0 - July 24, 2002 61/111 The Table 4-15 below refers to Vh, Va, Vs which are the register value for Setup time, Active Time and Hold time, as described in the Programming Manual. Table 4-15. Local Bus cycle lenght Cycle Tsetup Tactive Thold Tend Unit Memory (FCSx#) 4 + Vh 2 + Va 4 + Vs 4 HCLK Peripheral (IOCSx#) 4 + Vh 2 + Va 4 + Vs 4 HCLK Table 4-16. Local Bus Interface AC Timing Name Parameters Min Max Units HCLK to PA bus - 15 nS HCLK to PD bus - 15 nS HCLK to FCS#[1:0] - 15 nS HCLK to IOCS#[3:0] - 15 nS HCLK to PWR#, PRD# - 15 nS HCLK to BE#[1:0] - 15 nS PD[15:0] Input setup to HCLK - 4 nS PD[15:0] Input hold to HCLK 2 - nS PRDY Input setup to HCLK - 4 nS PRDY Input hold to HCLK 2 - nS |
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