STPC12GDYI datasheet(2/111 Pages) STMICROELECTRONICS

2 / 111 page

STPC

® ATLAS

2/111

Issue 1.0 - July 24, 2002

DESCRIPTION

The STPC Atlas integrates a standard 5th

generation x86 core along with a powerful UMA

graphics/video chipset, support logic including

PCI, ISA, Local Bus, USB, EIDE controllers and

combines them with standard I/O interfaces to

provide a single PC compatible subsystem on a

single device, suitable for all kinds of terminal and

industrial appliances.

X86 Processor core

Fully static 32-bit 5-stage pipeline, x86

processor fully PC compatible.

Can access up to 4GB of external memory.

8Kbyte unified instruction and data cache

with write back and write through capability.

Parallel processing integral floating point unit,

with automatic power down.

Runs up to 133 MHz (X2).

Fully static design for dynamic clock control.

Low power and system management modes.

Optimized design for 2.5V operation.

SDRAM Controller

64-bit data bus.

Up to 90MHz SDRAM clock speed.

Integrated system memory, graphic frame

memory and video frame memory.

Supports 8MB up to 128 MB system memory.

Supports 16-Mbit, 64-Mbit and 128-Mbit

SDRAMs.

Supports 8, 16, 32, 64, and 128 MB DIMMs.

Supports buffered, non buffered, and

registered DIMMs

4-line write buffers for CPU to DRAM and PCI

to DRAM cycles.

4-line read prefetch buffers for PCI masters.

Programmable latency

Programmable timing for SDRAM

parameters.

Supports -8, -10, -12, -13, -15 memory parts

Supports memory hole between 1MB and

8MB for PCI/ISA busses.

32-bit access, Autoprecharge & Power-down

are not supported.

Enhanced 2D Graphics Controller

Supports pixel depths of 8, 16, 24 and 32 bit.

Full BitBLT implementation for all 256 raster

operations defined for Windows.

Supports 4 transparent BLT modes - Bitmap

Transparency, Pattern Transparency, Source

Transparency and Destination Transparency.

Hardware clipping

Fast line draw engine with anti-aliasing.

Supports 4-bit alpha blended font for anti-

aliased text display.

Complete double buffered registers for

pipelined operation.

64-bit wide pipelined architecture running at

90 MHz. Hardware clipping

CRT Controller

Integrated 135MHz triple RAMDAC allowing

for 1280 x 1024 x 75Hz display.

8-, 16-, 24-bit pixels.

Interlaced or non-interlaced output.

Video Input port

Accepts video inputs in CCIR 601/656 mode.

Optional 2:1 decimator

Stores captured video in off setting area of

the onboard frame buffer.

HSYNC and B/T generation or lock onto

external video timing source.

Video Pipeline

Two-tap interpolative horizontal filter.

Two-tap interpolative vertical filter.

Color space conversion (RGB to YUV and

YUV to RGB).

Programmable window size.

Chroma and color keying for integrated video

overlay.

STPC12GDYI 数据表(PDF) 2 Page - STMicroelectronics

STPC12GDYI 数据表(HTML) 2 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

数据表下载