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STPC12GDYI 数据表(PDF) 52 Page - STMicroelectronics |
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STPC12GDYI 数据表(HTML) 52 Page - STMicroelectronics |
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52 / 111 page  ELECTRICAL SPECIFICATIONS 52/111 Issue 1.0 - July 24, 2002 4.5.4. PCI INTERFACE Figure 4-6 and Table 4-12 list the AC characteris- tics of the PCI interface. PCICLKx stands for any PCI device clock input. Figure 4-6. PCI Timing Diagram PCICLKI STPC.output STPC.input PCICLKx Tclkx Tsetup Thold Toutput (min) Toutput (max) Tcycle Thigh Tlow HCLK Thclk Table 4-12. PCI Bus AC Timings Name Parameter Min Typ Max Unit HCLK to PCICLKO delay (MD[30:27] = 1111) 4.4 5.0 5.7 ns Thclk HCLK to PCICLKI delay 6.5 7.5 8.5 ns Tclkx PCICLKI to PCICLKx skew -0.5 0.3 1.0 ns Tcycle PCICLKI Cycle Time 30 ns Thigh PCICLKI High Time 13 ns Tlow PCICLKI Low Time 13 ns PCICLKI Rising Time 1.5 ns PCICLKI Falling Time 1.5 ns PCICLKI to any output -ns Setup to PCICLKI -- ns Hold from PCICLKI -- ns HCLK to any output -ns Setup to HCLK -- ns Hold from HCLK -- ns Note: These timings are for a load of 50pF. |
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