STPCE1HDBC datasheet(19/87 Pages) STMICROELECTRONICS

19 / 87 page

PIN DESCRIPTION

Release 1.3 - January 29, 2002

19/87

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

RMRTCCS# ROM/Real Time clock chip select.

This signal is asserted if a ROM access is

decoded during a memory cycle. It should be

combined with MEMR# or MEMW# signals to

properly access the ROM. During a IO cycle, this

signal is asserted if access to the Real Time Clock

(RTC) is decoded. It should be combined with IOR

or IOW# signals to properly access the real time

clock.

KBCS#

Keyboard Chip Select. This signal is

asserted if a keyboard access is decoded during a

I/O cycle.

RTCRW# Real Time Clock RW. This pin is a multi-

function pin. When ISAOE# is active, this signal is

used as RTCRW#. This signal is asserted for any

I/O write to port 71H.

RTCDS# Real Time Clock DS. This pin is a multi-

function pin. When ISAOE# is active, this signal is

used as RTCDS# This signal is asserted for any I/

O read to port 71H. Its polarity complies with the

DS pin of the MT48T86 RTC device when

configured with Intel timings.

Note:

RMRTCCS#,

KBCS#,

RTCRW#

and

RTCDS# signals must be ORed externally with

ISAOE# and then connected to the external

device. An LS244 or equivalent function can be

used if OE# is connected to ISAOE# and the

output is provided with a weak pull-up resistor as

shown in Design Guidelines chapter.

2.2.6. LOCAL BUS

PA[23:0] Address Bus Output.

PD[15:0] Data Bus. This is the 16-bit data bus.

D[7:0] is the LSB and PD[15:8] is the MSB.

PRD#[1:0] Read Control output. PRD0# is used to

read the LSB and PRD1# to read the MSB.

PWR#[1:0] Write Control output. PWR0# is used

to write the LSB and PWR1# to write the MSB.

PRDY Data Ready input. This signal is used to

create wait states on the bus. When high, it

completes the current cycle.

FCS#[1:0] Flash Chip Select output. These are

the Programmable Chip Select signals for up to 2

banks of Flash memory.

IOCS#[3:0] I/O Chip Select output. These are the

Programmable Chip Select signals for up to 4

external I/O devices.

2.2.7. IDE INTERFACE

DA[2:0] Address. These signals are connected to

DA[2:0] of IDE devices directly or through a buffer.

If the toggling of signals are to be masked during

ISA bus cycles, they can be externally ORed with

ISAOE# before being connected to the IDE

devices.

DD[15:0]

Databus. When the IDE bus is active,

they serve as IDE signals DD[11:0]. IDE devices

are connected to SA[19:8] directly and ISA bus is

connected to these pins through two LS245

transceivers as described in Design Guidelines

chapter.

PCS1#, PCS3#

Primary Chip Select. These

signals are used as the active high primary master

& slave IDE chip select signals. These signals

must be externally ANDed with the ISAOE# signal

before driving the IDE devices to guarantee it is

active only when ISA bus is idle.

SCS1#, SCS3# Secondary Chip Select. These

signals are used as the active high secondary

master & slave IDE chip select signals. These

signals must be externally ANDed with the

ISAOE# signal before driving the IDE devices to

guarantee it is active only when ISA bus is idle.

DIORDY Busy/Ready. This pin serves as IDE

signal DIORDY.

PIRQ Primary Interrupt Request.

SIRQ Secondary Interrupt Request.

Interrupt request from IDE channels.

PDRQ Primary DMA Request.

SDRQ Secondary DMA Request.

DMA request from IDE channels.

PDACK# Primary DMA Acknowledge.

SDACK# Secondary DMA Acknowledge.

DMA acknowledge to IDE channels.

PDIOR#, PDIOW# Primary I/O Read & Write.

SDIOR#, SDIOW# Secondary I/O Read & Write.

Primary & Secondary channel read & write.

2.2.8. JTAG INTERFACE

TCLK Test clock

TDI Test data input

TMS Test mode input

TDO Test data output

2.2.9. MISCELLANEOUS

GPIO[15:0] General Purpose I/Os

SPKRD Speaker Drive. This the output to the

speaker and is an AND of the counter 2 output

with bit 1 of Port 61, and drives an external speak-

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