STPCE1HDBC datasheet(43/87 Pages) STMICROELECTRONICS

43 / 87 page

ELECTRICAL SPECIFICATIONS

Release 1.3 - January 29, 2002

43/87

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

4.5.6 ISA INTERFACE AC TIMING CHARACTERISTICS

Table 4-7 and Table 4-11 list the AC characteris-

tics of the ISA interface.

Figure 4-7 ISA Cycle (ref Table 4-11)

Note 1: Stands for SMEMR#, SMEMW#, MEMR#, MEMW#, IOR# & IOW#.

The clock has not been represented as it is dependent on the ISA Slave mode.

Valid AENx

Valid Address

Valid Address, SBHE*

V.Data

VALID DATA

ALE

AEN

LA [23:17]

SA [19:0]

CONTROL (Note 1)

IOCS16#

MCS16#

IOCHRDY

READ DATA

WRITE DATA

Table 4-11. ISA Bus AC Timing

Name

Parameter

Min

Max

Units

LA[23:17] valid before ALE# negated

Cycles

LA[23:17] valid before MEMR#, MEMW# asserted

3a Memory access to 16-bit ISA Slave

Cycles

3b Memory access to 8-bit ISA Slave

Cycles

SA[19:0] & SBHE valid before ALE# negated

Cycles

SA[19:0] & SBHE valid before MEMR#, MEMW# asserted

10a Memory access to 16-bit ISA Slave

Cycles

10b Memory access to 8-bit ISA Slave

Cycles

SA[19:0] & SHBE valid before SMEMR#, SMEMW# asserted

10c Memory access to 16-bit ISA Slave

Cycle

Note: The signal numbering refers to Table 4-7

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