STPCE1EEBI datasheet(28/87 Pages) STMICROELECTRONICS

28 / 87 page

STRAP OPTION

28/87

Release 1.3 - January 29, 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

3.1. POWER ON STRAP REGISTER DESCRIPTIONS

3.1.1. STRAP REGISTER 0 CONFIGURATION

Strap0

Access = 0022h/0023h

Regoffset = 04Ah

76543210

MD7

MD6

MD5

MD4

MD3

MD2

Rsv

This register defaults to the values sampled on MD[7:0] pins after reset

Bit Number Sampled

Mnemonic

Description

Bits 7-6

MD[7:6]

PCICLK Programming; the PCICLK PLL is setup through

MD[7:6]. The PLL setup will vary depending on the PCICLK

frequency. See Table 3-2 for details.

Bit 5

MD5

This bit reflects the value sampled on MD[5] pin and controls the MCLK/

HCLK Synchronization. When MCLK and HCLK frequency are the same,

when set to 1 it unifies HCLK and MCLK and so improves system

performance.

Bit 4

MD4

This bit reflects the value sampled on MD[4] pin and controls the

PCICLKO division. It works in conjunction with MD[17]; refer to Section

3.1.3. bit 1 for more details.

Bits 3-2

MD[3:2]

See Section 3.1.4.

Bits 1-0

Rsv

Reserved.

Table 3-2. PCI Clock Programming

Bit 7

Bit 6

Description

PCICLK frequency between 16 & 32 MHz

PCICLK frequency between 32 & 64 MHz

Reserved

STPCE1EEBI 数据表(PDF) 28 Page - STMicroelectronics

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