STPCE1EEBI datasheet(36/87 Pages) STMICROELECTRONICS

36 / 87 page

ELECTRICAL SPECIFICATIONS

36/87

Release 1.3 - January 29, 2002

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

4.5. AC CHARACTERISTICS

This section lists the AC characteristics of the

STPC interfaces including output delays, input

setup requirements, input hold requirements and

output float delays. These measurements are

based on the measurement points identified in

Figure 4-1 and Figure 4-2. The rising clock edge

reference level VREF and other reference levels

are shown in Table 4-7 below. Input or output

signals must cross these levels during testing.

Figure 4-1 shows output delay (A and B) and input

setup and hold times (C and D). Input setup and

hold times (C and D) are specified minimums,

defining the smallest acceptable sampling window

a synchronous input signal must be stable for

correct operation.

Note: Refer to Figure 4-1.

Table 4-7. Drive Level and Measurement Points for Switching Characteristics

Symbol

Value

Units

VREF

1.5

VIHD

2.5

VILD

0.0

Figure 4-1. Drive Level and Measurement Points for Switching Characteristics

CLK:

VRef

VILD

VIHD

LEGEND:

A - Maximum Output Delay Specification

B - Minimum Output Delay Specification

C - Minimum Input Setup Specification

D - Minimum Input Hold Specification

VRef

Valid

OUTPUTS:

INPUTS:

Output n

Output n+1

Input

MAX

MIN

VRef

VILD

VIHD

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