STPC0366BTC3 datasheet(18/51 Pages) STMICROELECTRONICS

18 / 51 page

PIN DESCRIPTION

18/51

Issue 1.2

2.2.7 ISA/IDE COMBINED CONTROL

IOCHRDY/DIORDY

Channel Ready (ISA)/Busy/

Ready (IDE). This is a multi-function pin. When

the ISA bus is active, this pin is IOCHRDY. When

the IDE bus is active, this serves as IDE signal DI-

ORDY.

IOCHRDY is the IO channel ready signal of the

ISA bus and is driven as an output in response to

an ISA master cycle targeted to the host bus or an

internal register of the STPC Consumer. The

STPC Consumer monitors this signal as an input

when performing an ISA cycle on behalf of the

host CPU, DMA master or refresh.

ISA masters which do not monitor IOCHRDY are

not guaranteed to work with the STPC Consumer

since the access to the system memory can be

considerably delayed due to CRT refresh or a

write back cycle.

2.2.8 ISA CONTROL

ALE

Address Latch Enable. This is the address

latch enable output of the ISA bus and is asserted

by the STPC Consumer to indicate that LA23-17,

SA19-0, AEN and SBHE# signals are valid. The

ALE is driven high during refresh, DMA master or

an ISA master cycles by the STPC Consumer.

ALE is driven low after reset.

BHE#

System Bus High Enable. This signal, when

asserted, indicates that a data byte is being trans-

ferred on SD15-8 lines. It is used as an input when

an ISA master owns the bus and is an output at all

other times.

MEMR#

Memory Read. This is the memory read

command signal of the ISA bus. It is used as an in-

put when an ISA master owns the bus and is an

output at all other times.

The MEMR# signal is active during refresh.

MEMW#

Memory Write. This is the memory write

command signal of the ISA bus. It is used as an in-

put when an ISA master owns the bus and is an

output at all other times.

SMEMR#

System Memory Read. The STPC Con-

sumer generates SMEMR# signal of the ISA bus

only when the address is below one megabyte or

the cycle is a refresh cycle.

SMEMW#

System Memory Write. The STPC Con-

sumer generates SMEMW# signal of the ISA bus

only when the address is below one megabyte.

This signal is multiplexed with COL_CMP on the

VGA Interface. The signal is selected by setting

Strap Option MD[0] as described in Section 3.

IOR#

I/O Read. This is the IO read command sig-

nal of the ISA bus. It is an input when an ISA mas-

ter owns the bus and is an output at all other

times.

IOW#

I/O Write. This is the IO write command sig-

nal of the ISA bus. It is an input when an ISA mas-

ter owns the bus and is an output at all other

times.

MASTER#

Add On Card Owns Bus. This signal is

active when an ISA device has been granted bus

ownership.

MCS16#

Memory Chip Select16. This is the de-

code of LA23-17 address pins of the ISA address

bus without any qualification of the command sig-

nal lines. MCS16# is always an input. The STPC

Consumer ignores this signal during IO and re-

fresh cycles.

IOCS16#

IO Chip Select16. This signal is the de-

code of SA15-0 address pins of the ISA address

bus without any qualification of the command sig-

nals. The STPC Consumer does not drive

IOCS16# (similar to PC-AT design). An ISA mas-

ter access to an internal register of the STPC Con-

sumer is executed as an extended 8-bit IO cycle.

REF#

Refresh Cycle. This is the refresh command

signal of the ISA bus. It is driven as an output

when the STPC Consumer performs a refresh cy-

cle on the ISA bus. It is used as an input when an

ISA master owns the bus and is used to trigger a

refresh cycle.

The STPC Consumer performs a pseudo hidden

refresh. It requests the host bus for two host

clocks to drive the refresh address and capture it

in external buffers. The host bus is then relin-

quished while the refresh cycle continues on the

ISA bus.

AEN

Address Enable. Address Enable is enabled

when the DMA controller is the bus owner to indi-

cate that a DMA transfer will occur. The enabling

of the signal indicates to IO devices to ignore the

IOR#/IOW# signal during DMA transfers.

ZWS#

Zero Wait State. This signal, when assert-

ed by addressed device, indicates that current cy-

cle can be shortened.

IOCHCK#

IO Channel Check. IO Channel Check

is enabled by any ISA device to signal an error

condition that can not be corrected. NMI signal be-

comes active upon seeing IOCHCK# active if the

corresponding bit in Port B is enabled.

STPC0366BTC3 数据表(PDF) 18 Page - STMicroelectronics

STPC0366BTC3 数据表(HTML) 18 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

数据表下载