STPC0366BTC3 datasheet(28/51 Pages) STMICROELECTRONICS

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STRAP OPTION

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Issue 1.2

Note;

1) This Strap Option selects between two different

functional blocks, the first is the ISA (SMEMW#)

and the other is the VGA block (Color_Key).

2) Setting of Strap Options MD [2:15] have no ef-

fect on the DRAM Controller but are purely meant

for software issues. i.e. Readable in a register.

3.1 STRAP REGISTER DESCRIPTION

3.1.1

STRAP

INDEX

4AH

(STRAP0)

Bits 7-0 of this register reflect the status of pins

MD[7:0] respectively. They are expected to be

connected on the system board to the SIMM con-

figuration pins as follows:

Note that the SIMM speed and type information

read here is meant only for the software and is not

used by the hardware. The software must pro-

gram the Host and graphics dram controller con-

figuration registers appropriately based on these

bits.

This register defaults to the values sampled on

MD[7:0] pins after reset.

3.1.2

STRAP

INDEX

4BH

(STRAP1)

Bits 7-0 of this register reflect the status of pins

MD[15:8] respectively. They are expected to be

connected on the system board to the SIMM con-

figuration pins as follows:

Note that the SIMM speed and type information

read here is meant only for thesoftware and is not

used by the hardware. The software must pro-

gram the Host and graphics dram controller con-

figuration registers appropriately based on these

bits.

This register defaults to the values sampled on

MD[15:8] pins after reset.

3.1.3

STRAP

INDEX

4CH

(STRAP2)

Bits 4-0 of this register reflect the status of pins

MD[20:16] respectively. Bit 5 of this register reflect

the status of pin MD[23]. Bit 4 is writeable, writes

to other bits in this register have no effect.

They are use by the chip as follows:

Bit 4-2; Reserved

MD38

Reserved

Pull up

MD39

Reserved

Pull up

MD40

CPU

CPU Mode

User defined

DX1

DX2

MD41

Reserved

Pull down

MD42

Reserved

Pull up

MD43

Reserved

Pull down

Memory

Data

Lines

Note

Refer to

Designation

Location

Actual

Settings

Set to ’0’

Set to ’1’

Bit Sampled

Description

Bit 7

SIMM 0 dram type

Bits 6-5

SIMM 0 speed

Bit 4

SIMM 1 dram type

Bits 3-2

SIMM 1 speed

Bits 1-0

Reserved

Bit Sampled

Description

Bit 7

SIMM 2 dram type

Bits 6-5

SIMM 2 speed

Bit 4

SIMM 3 dram type

Bits 3-2

SIMM 3 speed

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