STPC12 datasheet(50/111 Pages) STMICROELECTRONICS

50 / 111 page

ELECTRICAL SPECIFICATIONS

50/111

Issue 1.0 - July 24, 2002

4.5.3. SDRAM INTERFACE

Figure 4-5, Table 4-10, Table 4-11 lists the AC

characteristics of the SDRAM interface. The

MCLKx clocks are the input clock of the SDRAM

devices.

The PC100 memory is recommended to reach

90MHz operation.

Figure 4-5. SDRAM Timing Diagram

MCLKI

STPC.output

STPC.input

MCLKx

Tdelay

Tsetup

Thold

Toutput (min)

Toutput (max)

Tcycle

Thigh

Tlow

Table 4-10. SDRAM Bus AC Timings - Commercial Temperature Range

Name

Parameter

Min

Typ

Max

Unit

Tcycle

MCLKI Cycle Time

Thigh

MCLKI High Time

Tlow

MCLKI Low Time

MCLKI Rising Time

MCLKI Falling Time

Tdelay

MCLKx to MCLKI delay

2.1

Toutput

MCLKI to RAS# Valid

1.6

5.2

MCLKI to CAS# Valid

1.6

5.2

MCLKI to CS# Valid

1.6

5.2

MCLKI to DQM[ ] Outputs Valid

1.35

5.2

MCLKI to MD[ ] Outputs Valid

1.35

5.2

MCLKI to MA[ ] Outputs Valid

1.6

5.2

MCLKI to MWE# Valid

1.6

5.2

Tsetup

MD[63:0] setup to MCKLI

7.5

Thold

MD[63:0] hold from MCKLI

-0.36

Note: These timings are for a load of 50pF, part running at 100MHz and ReadCLK not activated

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