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STPC0380BTI3 数据表(PDF) 32 Page - STMicroelectronics |
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STPC0380BTI3 数据表(HTML) 32 Page - STMicroelectronics |
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32 / 51 page  ELECTRICAL SPECIFICATIONS 32/51 Issue 1.2 Figure 4-1 Drive Level and Measurement Points for Switching Characteristics Figure 4-2 CLK Timing Measurement Points Note; The above timings are generic timings and are not specific to the interfaces defined below CLK: VRef VILD VIHD Tx LEGEND: A - Maximum Output Delay Specification B - Minimum Output Delay Specification C - Minimum Input Setup Specification D - Minimum Input Hold Specification VRef Valid Valid Valid OUTPUTS: INPUTS: Output n Outp ut n+1 Input MAX MIN A B CD VRef VILD VIHD CLK T5 T4 T3 VRef VIL (MAX) VIH (MIN) T2 T1 LEGEND: T1 - One Clock Cycle T2 - Minimum Time at VIH T3 - Minimum Time at VIL T4 - Clock Fall Time T5 - Clock Rise Time NOTE; All sIgnals are sampled on the rising edge of the CLK. |
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