M41ST87YMX6 datasheet(17/48 Pages) STMICROELECTRONICS

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M41ST87Y, M41ST87W

Operating modes

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power input is switched from the VCC pin to the battery, and the clock registers and external

SRAM are maintained from the attached battery supply.

All outputs become high impedance. The VOUT pin is capable of supplying 100µA (for

M41ST87W) or 150µA (for M41ST87Y) of current to the attached memory with less than 0.3

volts drop under this condition. On power up, when VCC returns to a nominal value, write

protection continues for trec by inhibiting ECON. The RST signal also remains active during

this time (see Figure 27 on page 43).

Note:

Most low power SRAMs on the market today can be used with the M41ST87Y/W RTC

SUPERVISOR. There are, however some criteria which should be used in making the final

choice of an SRAM to use. The SRAM must be designed in a way where the chip enable

input disables all other inputs to the SRAM. This allows inputs to the M41ST87Y/W and

SRAMs to be “Don’t Care” once VCC falls below VPFD(min). The SRAM should also

guarantee data retention down to VCC = 2.0 volts. The chip enable access time must be

sufficient to meet the system needs with the chip enable output propagation delays

included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to

VOUT.

If data retention lifetime is a critical parameter for the system, it is important to review the

data retention current specifications for the particular SRAMs being evaluated. Most SRAMs

specify a data retention current at 3.0 volts. Manufacturers generally specify a typical

condition for room temperature along with a worst case condition (generally at elevated

temperatures). The system level requirements will determine the choice of which value to

use. The data retention current value of the SRAMs can then be added to the IBAT value of

the M41ST87Y/W to determine the total current requirements for data retention. The

available battery capacity for the battery of your choice can then be divided by this current to

determine the amount of data retention available.

For a further more detailed review of lifetime calculations, please see Application Note

AN1012.

2.5

Tamper detection circuit

The M41ST87Y/W provides two independent input pins, the tamper pin 1 input (TP1IN) and

tamper pin 2 input (TP2IN), which can be used to monitor two separate signals which can

result in the associated setting of the tamper bits (TB1 and/or TB2, in flag register 0Fh) if the

tamper enable bits (TEB1 and/or TEB2) are enabled, for the respective tamper 1 or tamper

2. The TP1IN pin or TP2IN pin may be set to indicate a tamper event has occurred by either

1) closing a switch to ground or VOUT (normally open), or by 2) opening a switch that was

previously closed to ground or VOUT (normally closed), depending on the state of the TCMX

bits and the TPMX bits in the tamper register (14h and/or 15h).

2.6

Tamper register bits (tamper 1 and tamper 2)

2.6.1

Tamper enable bits (TEB1 and TEB2)

When set to a logic '1,' this bit will enable the tamper detection circuit. This bit must be set to

'0' in order to clear the associated tamper bits (TBX, in 0Fh).

Note:

TEBX should be reset whenever the tamper detect condition is modified.

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