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M41ST87YMX6 数据表(PDF) 34 Page - STMicroelectronics |
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M41ST87YMX6 数据表(HTML) 34 Page - STMicroelectronics |
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34 / 48 page ![]() Clock operation M41ST87Y, M41ST87W 34/48 3.4 Watchdog timer The watchdog timer can be used to detect an out-of-control microprocessor. The user programs the watchdog timer by setting the desired amount of time-out into the watchdog register, address 09h. Bits BMB4-BMB0 store a binary multiplier and the two lower order bits RB1-RB0 select the resolution, where 00=1/16 second, 01=1/4 second, 10=1 second, and 11=4 seconds. The amount of time-out is then determined to be the multiplication of the five- bit multiplier value with the resolution. (For example: writing 00001110 in the watchdog register = 3*1 or 3 seconds). Note: The accuracy of the timer is within ± the selected resolution. If the processor does not reset the timer within the specified period, the M41ST87Y/W sets the WDF (watchdog flag) and generates a watchdog interrupt or a microprocessor reset. The most significant bit of the watchdog register is the watchdog steering bit (WDS). When set to a '0,' the watchdog will activate the IRQ/OUT pin when timed-out. When WDS is set to a '1,' the watchdog will output a negative pulse on the RST pin for trec. The watchdog register, FT, AFE, ABE and SQWE bits will reset to a '0' at the end of a watchdog time-out when the WDS bit is set to a '1.' The watchdog timer can be reset by two methods: 1) a transition (high-to-low or low-to-high) can be applied to the watchdog input pin (WDI) or 2) the microprocessor can perform a WRITE of the watchdog register. The time-out period then starts over. Note: The WDI pin should be tied to VSS if not used. In order to perform a software reset of the watchdog timer, the original time-out period can be written into the watchdog register, effectively restarting the count-down cycle. Should the watchdog timer time-out, and the WDS bit is programmed to output an interrupt, either a transition of the WDI pin, or a value of 00h needs to be written to the watchdog register in order to clear the IRQ/OUT pin. This will also disable the watchdog function until it is again programmed correctly. A READ of the flags register will reset the watchdog flag (bit D7; register 0Fh). The watchdog function is automatically disabled upon power-up and the watchdog register is cleared. 3.5 Square wave output The M41ST87Y/W offers the user a programmable square wave function which is output on the SQW/FT pin. RS3-RS0 bits located in 13h establish the square wave output frequency. These frequencies are listed in Table 9. Once the selection of the SQW frequency has been completed, the SQW/FT pin can be turned on and off under software control with the square wave enable bit (SQWE) located in Register 0Ah. The SQW/FT output is programmable as an N-channel, open drain output driver, or a full- CMOS output driver. By setting the square wave open drain bit (SQWOD) to a '1,' the output will be configured as an open drain (with IOL as specified in Table 17 on page 42). When SQWOD is set to '0,' the output will be configured as full-CMOS (sink and source current as specified in Table 17 on page 42). Note: When configured as open drain (SQWOD = '1'), the SQW/FT pin requires an external pull- up resistor. |
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