MSC7119 datasheet(21/60 Pages) FREESCALE

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Electrical Characteristics

MSC7119 Data Sheet, Rev. 8

Freescale Semiconductor

2.5

AC Timings

This section presents timing diagrams and specifications for individual signals and parallel I/O outputs and inputs. All AC

timings are based on a 30 pF load, except where noted otherwise, and a 50

Ω transmission line. For any additional pF, use the

following equations to compute the delay:

— Standard interface: 2.45 + (0.054

× C

load) ns

— DDR interface: 1.6 + (0.002

× C

load) ns

2.5.1

Clock and Timing Signals

The following tables describe clock signal characteristics. Table 6 shows the maximum frequency values for internal (core,

reference, and peripherals) and external (CLKO) clocks. You must ensure that maximum frequency values are not exceeded (see

Section 2.5.2 for the allowable ranges when using the PLL).

Table 6. Maximum Frequencies

Characteristic

Maximum in MHz

Core clock frequency (CLOCK)

300

External output clock frequency (CLKO)

Memory clock frequency (CK, CK)

150

TDM clock frequency (TxRCK, TxTCK)

Table 7. Clock Frequencies in MHz

Characteristic

Symbol

Min

Max

CLKIN frequency

FCLKIN

100

CLOCK frequency

FCORE

—

300

CK, CK frequency

FCK

—

150

TDMxRCK, TDMxTCK frequency

FTDMCK

—50

CLKO frequency

FCKO

—75

AHB/IPBus/APB clock frequency

FBCK

—

150

Note:

The rise and fall time of external clocks should be 5 ns maximum

Table 8. System Clock Parameters

Characteristic

Min

Max

Unit

CLKIN frequency

100

MHz

CLKIN slope

—5

CLKIN frequency jitter (peak-to-peak)

—

1000

CLKO frequency jitter (peak-to-peak)

—

150

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