HD151TS201AT

Rev.1.00, Oct.21.2003, page 11 of 28

I

Byte8 Clock Frequency Control Register

Bit

Description

Contents

Default

7

Reserved

X

6

Reserved

X

5

Reserved

0

4

Reserved

0

3

Clock Freq. Control bit2

0

2

Clock Freq. Control bit1

0

1

Clock Freq. Control bit0

See Table1

0

0

Freq. Select Mode bit

0 = Freq. is selected by latched input S2:0

1 = Freq. is selected by I

0

Byte9 Control Register

Bit

Description

Contents

Default

7

Reserved

0

6

Reserved

0

5

Reserved

0

4

Reserved

0

3

Spread Spectrum Control bit

0 = –0.5% (Default)

1 = –1.0%

0

2

3V66 & PCI Clock PLL select bit

“0” = CPU PLL

“1” = USB PLL

When this bit set to “1”, 3V66 & PCI clocks will

be supply from USB PLL. Not depended on

CPU PLL.

0

1

PLL N Divider Control bit9

PLL N Divider Control bit9

0

0

PLL N Divider Control bit8

PLL N Divider Control bit8

0

Note:

Byte9 [1:0], Byte10 and Byte11must be written together (at writing Byte11) in every case.