HD151TS201AT datasheet(18/29 Pages) RENESAS

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HD151TS201AT

Rev.1.00, Oct.21.2003, page 18 of 28

Pin Descriptions

Pin name

No.

Type

Description

GND

4,9,15,20

31,36,41,47

Ground

GND pins

VDD

1,8,14,19

32,37,46,50

Power

Power supplies pins. Nominal 3.3 V.

VDDA

Power

Power supply for PLL core.

GNDA

Power

Power supply for PLL core.

CPUT[2:0]

45,49,52

OUTPUT

“True” clocks of differential pair CPUCLK.

These pins are HCSL output.

CPUC[2:0]

44,48,51

OUTPUT

“Complementary” clocks of differential pair CPUCLK.

These pins are HCSL output.

CPUSTOP#

INPUT

CPUCLK STOP pin. Active low input.

When asserted low, CPUT [2:0] clocks are synchronously

disabled in high state and CPUC [2:0] clocks are synchronously

disabled in a low state.

CPUSTOP# pin is 150 k

Ω internal pulled-up.

PCIF[2:0]

7,6,5

OUTPUT

Free running PCI clock 3.3 V output.

33 MHz clocks divided from 3V66.

PCI[6:0]

18,17,16,13

12,11,10

OUTPUT

3.3 V PCI clock outputs.

33 MHz clocks divided from 3V66.

PCISTOP#

INPUT

PCICLK STOP pin. Active low input.

When asserted low, PCI [6:0] clocks are synchronously

disabled in low state. This pin does not effect PCIF [2:0] clocks

outputs if they are programmed to be PCIF clocks via the

device’s SM Bus interface.

PCISTOP# pin is 150 k

Ω internal pulled-up.

S1, S0

55,54

INPUT

Frequency selects input. See frequency table2 in page5.

INPUT

Frequency selects input. See frequency table2 in page5.

This pin is 3 level input.

VTT_PWRGD#

INPUT

Qualifying input that latches S [2:0] and MULT0. When this

input is at a logic low, the S[2:0] and MULT0 are latched.

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