HD151TS207SS datasheet(9/38 Pages) RENESAS

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HD151TS207SS

Rev.1.00, Apr.25.2003, page 9 of 38

2C Controlled Register Bit Map (cont.)

Table4 CPU Clock Power Management Truth Table

Signal

PWRDWN#

Tristate Bit

Byte2[5:3]

Non-Stop

Outputs

Byte1[5:3] = 1

Note

CPU[2:0]

Running

CPU[2:0]

Driven @ Iref x2

See Note1

CPU[2:0]

Tristate

Note:

1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA,

Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50

Ω)

Table5 SRC Clock Power Management Truth Table

Signal

PWRDWN#

PCI_STOP#

Tristate Bit

Byte2[6]

PWRDWN#

Tristate Bit

Byte2[7]

Non-Stop

Outputs

Byte1[7] = 1

Stoppable

Outputs

Byte1[7] = 0

Note

SRC

Running

SRC

100X

Running

Driven @

Iref x6

See Note1

SRC

101X

Running

Tristate

SRC

Driven @

Iref x2

Driven @

Iref x2

See Note1

SRC

Tristate

Note:

1. Iref = VDD/(3Rr) = 3.3/(3x475) = 2.32 mA

Iref x6 = 13.9 mA (Voh @Z: 0.7 V @50

Ω)

Iref x2 = 4.6 mA (Voh @Z: 0.23 V @50

Ω)

Byte3 Control Register

Bit

Description

Contents

Type

Default

Note

PCI_Stop control

0 = Enabled, all stoppable PCI

and SRC clocks are stopped.

1 = Disabled

PCI_6 Output enable

0 = Disabled, 1 = Enabled

PCI_5 Output enable

0 = Disabled, 1 = Enabled

PCI_4 Output enable

0 = Disabled, 1 = Enabled

PCI_3 Output enable

0 = Disabled, 1 = Enabled

PCI_2 Output enable

0 = Disabled, 1 = Enabled

PCI_1 Output enable

0 = Disabled, 1 = Enabled

PCI_0 Output enable

0 = Disabled, 1 = Enabled

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