ELECTRICAL CHARACTERISTICS

Symbol

Parameter

Test Conditions

Min.

Typ.

Max.

Unit

8 BITS ADC & OB CLAMP

OB_rise

OB High Time Constant

Pin 38, OB 0 to 1

4

mV/

µs

OB_decay

OB Low Time Constant

Pin 38, OB 1 to 0

-2

mV/ms

BLK_RAN

Black Level Adjust Range

Pins 8 to 15, OB high,

Serial bus from H00 to H1F

31

LSBs

BLK_res

Black Level Adjust Resolution

Pins 8 to 15, per serial bus LSB step

1

LSBs

BLK_LEV

Black Level Adjust

Pins 8 to 15

Bus = H00

Bus = H1F

29

0

31

2

33

LSBs

LSBs

ADC_DN

ADC Input Dynamic Range (output

from 0 to 255)

Pin 38 test signal above black

1.4

1.55

1.7

ADC Clock Frequency

Pin 24

12

MHz

Output Pipeline Delay (3)

From a sampling to data out

3

3

CLK

cycles

Clock to Data Out (4)

17

ns

Ladder Resistance

Between Pins 36 and 37

330

Ω

Top Reference Voltage

Pin 36

3.2

3.35

3.5

V

Bottom Reference Voltage

Pin 37

1.71

1.8

1.89

V

ADC_lin

ADC Linearity

Data out, input signal between

1%

Notes : 3. The signal is being sampled as long as ADC_CLK is high.

4. See Figure 6 for data reading timing constraint.

Sampling

Period

Pixel N

Data available

on falling edge of clock

t

DADC

Pixel N-4

Pixel N-3

Pixel N-2

Pixel N-1

Pixel N

ADC_IN

ADC_CLOCK

DATA_OUT

Pixel N+1

Figure 6

edge of the ADC clock.

STV0502

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