FUNCTIONAL DESCRIPTION (continued)

3 - Serial Bus Specification

It is a 2-wires (data and clock) serial bus, used as

a slave.

Clock line is monodirectional (input) and allways

sent by the master to the chip, whereas Data line

is bidirectional (I/O).

There are 3 registers (8 bits), both writable/readable.

Each register can be addressed by a 4 bits address

word, followed by a R/W bit, and an 8 bits word Data

(read/write).

2 main patterns can be sent : Reset Pattern and

Read/Write pattern.

3.1 -Timings and Protocol

The data bit is taken into account when the clock

is rising.

- Reset Pattern : resets all the registers to their

default (Power On) values :

format = 16 * (data=1) | 2 * (data=0)

(total = 18 clocks)

- Read/Write Pattern :

format = 4 addr bits | R/W bit | 8 data bits

(total = 13 clocks)

Please note that :

1/ On power On conditions, SDATA line is in Write

(Input) Mode.

2/ In case of a read pattern, the SDATA line is

automatically set to Read (Output mode) during

8 clock cycles (Data D7 - D0) after R/W bit has

been sent, and comes back in Write (Input

mode) after the 13th clock cycle.

3/ There is no timing restriction between two

consecutive patterns (a pattern being defined

as one of the two above).

3.2 - Register Summary

Register

Address

(A3-A0)

Data Format

(D7-D0)

Video Amplifier Gain

0000

DDDD.DDDD

Black Level Adjust

0001

XXXD.DDDD

Video High Gain Select

0001

XXDX.XXXX

Test Mode

0001

DDXX.XXXX

Microphone AGC

0010

XXXX.XXXD

X

: unused bits

D

: means useful bits

Please note that 3 different functions are merged

in register address 01.

CLK

SDATA

Reset Pattern

1

2

3

4

5

6

7

8

9

10111213141516

1

2

2 CLK Cycles

Minimum 16 CLK Cycles

Figure 3

CLK

SDATA

Read/Write Pattern

A3

A2

A1

A0

R/W

D7

D6

D5

D4

D3

D2

D1

D0

123456789

10

11

12

13

Figure 4

STV0502

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