CDS_IN

FCDS

t1

t2

t4

t3

t

PROP

t

DADC

Pixel N

3 CLK Pipe-Line Delay

FS

CDS_OUT

ADC_IN

ADC_CLOCK

DATA_OUT

Sampling

Period

Pixel N+1

Pixel N+2

Pixel N+3

Pixel N+4

Pixel N+5

Pixel N-4

Pixel N-3

Pixel N-2

Pixel N-1

Pixel N

Pixel N+1

Pixel N

Pixel N+1

Pixel N+2

Pixel N+3

Pixel N+4

Notation :

- t1 is the delay between the falling edge of FCDS and the beginning of the active pixel level from the CCD.

- t2 is the delay between the falling edge of FS and the end of the active pixel level from the CCD.

t1, t2, t3 and t4 must be kept > 0 in the Application.

Figure 1

FUNCTIONAL DESCRIPTION (continued)

It is followed by a Voltage Controlled Amplifier

(range 8dB - 34dB), that can be switched into a

fixed 26dB gain amplifier.

The VCA output is differential and 2 buffers are

driving the two output pins, with a load impedance

down to 5k

Ω.

A bias circuitry and an external capacitor (ACC)

form a DC feedback loop on the VCA DC bias, in

order to correct any DC offset on the VCA output.

Finally, a peak detector (double alternance) is used

to compare the output signal with the reference

threshold, to be regulated at. An external capacitor

(CAGC) is used for the AGC time constants. If the

signal goes above the threshold, a 500

µA current

is charging the capacitor with a fast reponse

time(attack). In case of very big signals, a second

charge cureent of about 5mA is given, in order to

reduce the period during which the output signal is

saturated. Otherwise, a constant 1

µA current dis-

charges the capacitor with a slow response time

(decay). The capacitor voltage controls the VCA

gain. This constitues the AGC loop.

FS

CDS_OUT

FCDS

CDS_IN =

CCD Signal

Feedtrough Level

Signal Level

Figure 2

STV0502

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