PIN ASSIGNMENT (PQFP100)

Pin Number

Symbol

Type

Function

100

Supply

5V Logic Supply

1 - 29 - 30 - 51 - 52 - 80

Supply

High Voltage Supply of power outputs

6 - 15 - 24 - 35 - 40

46 - 57 - 66 - 75

Ground Ground of power outputs

90 to 93

Ground Logic Ground

41 - 81

Ground Substrate Ground

2 to 5 - 7 to 14 - 16 to 23

25 to 28 - 31 to 34 - 36 to 39

42 to 45 - 47 to 50 - 53 to 56

58 to 65 - 67 to 74 - 76 to 79

OUT1 to OUT 64

Output

Power Output

95

CLK

Input

Clock of data shift register

Low to High transition makes the data enter into the shift

register and available at the output stage and at the output

of the shift register.

94

STB

Input

Latch of data to outputs

When the STB signal is set to low level, data are transferred

into the latch stage. When STB is set at high level, data are

held in the latch stage.

88

BLK

Input

Power Output Blanking Control

87

POL

Input

Power Output Polarity Control

86

HIZ

Input

Power Output High Impedance Control

89

F/R

Input

Selection of shift direction

96 to 99

A4 to A1

Input

Shift register data input and output according to F/R value.

When set to low, Ai = input and Bi = output.

82 to 85

B1 to B4

Output

PIN ASSIGNMENT (Power Outputs)

Output N°

Pin N°

Output N°

Pin N°

Output N°

Pin N°

Output N°

Pin N°

1

2

17

20

33

42

49

62

2

3

18

21

34

43

50

63

3

4

19

22

35

44

51

64

4

5

20

23

36

45

52

65

5

7

21

25

37

47

53

67

6

8

22

26

38

48

54

68

7

9

23

27

39

48

55

69

8

102428

4050

5670

9

112531

4153

5771

10

12

26

32

42

54

58

72

11

13

27

33

43

55

59

73

12

14

28

34

44

56

60

74

13

16

29

36

45

58

61

76

14

17

30

37

46

59

62

77

15

18

31

38

47

60

63

78

16

19

32

39

48

61

64

79

STV7699

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