CIRCUIT DESCRIPTION

The STV7699 contains all the logic and the power

circuits necessary to drive the colums of a Plasma

Display Panel (P.D.P.). Data are shifted at each low

to high transition of the (CLK) shift clock. Data are

input in a 4-bit wide data bus to A1 - A4 input (case

of forward shift mode ; F/R = low). After 16 shifts,

the first nibble is available at the serial outputs

B1 - B4. These outputs can be used to cascade

several drivers to performed any horizontal resolu-

tion. CLK, Ai and Bi inputs are Smith trigger inputs

to improve the noise margin.

The Forward/Reverse (F/R) input is used to select

the direction of the shift register.

The maximum frequency of the shift clock is

20MHz.

All the output data are held and memorized into the

latch stage when the Latch input (STB) is high.

When it is at low level, data are transferred from

the shift register to the latch and to the output power

stage.

Output state can be forced to high impedance by

pulling low HIZ input.

When BLK is Low, all the outputs are forced to low

level or high level according to POL signal value.

Output state copy data that was input, with the

same polarity, when BLK, HIZ and POL are High.

nected.

possible to the logical reference ground of the

application.

Table 1 : Power Output Truth Table

Data STB POL BLK HIZ

Driver

Output

Comments

x

xxx

L

HIZ

High impedance

x

x

L

x

H

L

Forced to low

x

x

H

L

H

H

Forced to high

x

H

H

H

H

Qn (1)

Latched data

L

L

H

H

H

L

Copy data

H

L

H

H

H

H

Copy data

Note 1 : Qn is the value memorised in the latch stage ; it is the value

of the parallel shift register output stage after n Clock

pulses.

A data loaded in the shift register is read on the

output power stage without inversion of its polarity.

Table 2 : Control Table

F/R

Ai

Bi

Comments

L

Input

Output

Forward shift

H

Output

Input

Reverse shift

B4

A4

85

96

B3

A3

84

97

B2

A2

83

98

16-BIT SHIFT REGISTER

P3

P63

F/R

89

16-BIT SHIFT REGISTER

P1

P61

2

79

V

SSP

Pins 6-15-24-35

40-46-57-66-75

V

CC

B1

A1

STB

BLK

POL

OUT1

OUT64

STV7699

95

82

94

88

87

99

CLK

V

PP

Pins 1-29-30

51-52-80

LATCH

Q1

Q64

Q2

Q63

P64

P1

P63

P4

16-BIT SHIFT REGISTER

P2

P62

16-BIT SHIFT REGISTER

P4

P64

100

V

SSSUB

Pins 41-81

V

SSLOG

Pins 90 to 93

86

HIZ

BLOCK DIAGRAM

STV7699

4/9