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STV7699 数据表(PDF) 6 Page - STMicroelectronics |
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STV7699 数据表(HTML) 6 Page - STMicroelectronics |
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6 / 9 page  AC TIMINGS REQUIREMENTS (VCC = 4.5V to 5.5V, Tamb = -20 to +85°C, input signals max leading edge & trailing edge (tR, tF) = 10ns) Symbol Parameter Min. Typ. Max. Unit tCLK Data Clock Period 50 - - ns tWHCLK Duration of clock (CLK) pulse at high level 15 - - ns tWLCLK Duration of clock (CLK) pulse at low level 15 - - ns tSDAT Set-up Time of data input before clock (low to high) transition 0 - - ns tHDAT Hold Time of data input after clock (low to high) transition 15 - - ns tDSTB Minimum Delay to latch (STB) after clock (low to high) transition 20 - - ns tSTB Latch (STB) Low Level Pulse Duration 10 - - ns tBLK Blanking (BLK) Pulse Duration 100 - - ns tPOL Polarity (POL) Pulse Duration 100 - - ns tHIZ High Impedance (HIZ) Pulse Duration 100 - - ns tSFR Set-up Time of Forward/Reverse Signal before Clock (low to high) transition 100 - - ns AC TIMING CHARACTERISTICS (VCC = 5V, VPP = 65V, VSSP = 0V, VSSLOG = 0V, VSSSUB = 0V, Tamb = 25°C, VILMax. = 0.2VCC, VIHMin. = 0.8VCC, VOH = 4.0V, VOL = 0.4V, CL = 10pF, unless otherwise specified) Symbol Parameter Min. Typ. Max. Unit tCLK Data Clock Period 50 - - ns tRDAT Logical Data Output Rise Time - TBD 30 ns tFDAT Logical Data Output Fall Time - TBD 30 ns tPHL1 tPLH1 Delay of logic data output (high to low transition) after clock (CLK) transition Delay of logic data output (low to high transition) after clock (CLK) transition - - 40 40 TBD TBD ns ns tPHL2 tPLH2 Delay of power output change (high to low transition) after clock (CLK) transition Delay of power output change (low to high transition) after clock (CLK) transition - - TBD TBD 120 120 ns ns tPHL3 tPLH3 Delay of power output change (high to low transition) after Latch (STB) transition Delay of power output change (low to high transition) after Latch (STB) transition - - TBD TBD 110 110 ns ns tPHL4 tPLH4 Delay of power output change (high to low transition) to Blank (BLK) or Polarity (POL) transition Delay of power output change (low to high transition) to Blank (BLK) or Polarity (POL) transition - - TBD TBD 100 100 ns ns tPHZ5 tPLZ5 Delay of power output change (high to Hi-Z transition) after high impedance (HIZ) (5) Delay of power output change (low to Hi-Z transition) after high impedance (HIZ) (5) - - TBD TBD 100 100 ns ns tPZH5 tPZL5 Delay of power output change (Hi-Z to high transition) after high impedance (HIZ) (5) Delay of power output change (Hi-Z to low transition) after high impedance (HIZ) (5) - - TBD TBD 100 100 ns ns tROUT Power Output Rise Time (6) - - 150 ns tFOUT Power Output Fall Time (6) - - 150 ns Notes : 5. See test diagram. 6. One output among 64, loading capacitor COUT = 50pF, other outputs at low level. STV7699 6/9 |
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